traffic.vho

vhdl实现的交通灯

	combout => hz_a124_combout);

hz_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => clk_acombout,
	dataout => hz_CLK_driver);

hz_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => hz_DATAA_driver);

hz_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con(9),
	dataout => hz_DATAB_driver);

hz_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_a122_combout,
	dataout => hz_DATAC_driver);

hz_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_a124_combout,
	dataout => hz_DATAD_driver);

hz : cyclone_lcell
-- Equation(s):
-- hz_aregout = DFFEAS(hz_a122_combout & (hz_a124_combout & (con(9)) # !hz_a124_combout & hz_aregout) # !hz_a122_combout & hz_aregout, GLOBAL(clk_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "caaa",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => hz_CLK_driver,
	dataa => hz_DATAA_driver,
	datab => hz_DATAB_driver,
	datac => hz_DATAC_driver,
	datad => hz_DATAD_driver,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => hz_aregout);

rst_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_rst,
	combout => rst_acombout);

temp_a1_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => temp_a1_a_CLK_driver);

temp_a1_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => temp_a1_a_DATAC_driver);

temp_a1_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(1),
	dataout => temp_a1_a_DATAD_driver);

temp_a1_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => temp_a1_a_ACLR_driver);

temp_a1_a_ENA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => temp_a1_a_ENA_driver);

temp_a1_a : cyclone_lcell
-- Equation(s):
-- temp(1) = DFFEAS(temp(0) $ temp(1), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , Equal8_a71_combout, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0ff0",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => temp_a1_a_CLK_driver,
	datac => temp_a1_a_DATAC_driver,
	datad => temp_a1_a_DATAD_driver,
	aclr => temp_a1_a_ACLR_driver,
	ena => temp_a1_a_ENA_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => temp(1));

d1_a0_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d1_a0_a_CLK_driver);

d1_a0_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => d1_a0_a_DATAA_driver);

d1_a0_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d1_a0_a_DATAB_driver);

d1_a0_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a0_a_DATAC_driver);

d1_a0_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(0),
	dataout => d1_a0_a_DATAD_driver);

d1_a0_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d1_a0_a_ACLR_driver);

d1_a0_a : cyclone_lcell
-- Equation(s):
-- d1(0) = DFFEAS(Equal8_a71_combout & !temp(0) & (p2_a62_combout # !d1(0)) # !Equal8_a71_combout & (d1(0)), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "2f30",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d1_a0_a_CLK_driver,
	dataa => d1_a0_a_DATAA_driver,
	datab => d1_a0_a_DATAB_driver,
	datac => d1_a0_a_DATAC_driver,
	datad => d1_a0_a_DATAD_driver,
	aclr => d1_a0_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d1(0));

d1_a1337_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(1),
	dataout => d1_a1337_DATAA_driver);

d1_a1337_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(0),
	dataout => d1_a1337_DATAB_driver);

d1_a1337_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a1337_DATAC_driver);

d1_a1337_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => d1_a1337_DATAD_driver);

d1_a1337 : cyclone_lcell
-- Equation(s):
-- d1_a1337_combout = Equal8_a71_combout & (p2_a62_combout # d1(1) $ d1(0)) # !Equal8_a71_combout & d1(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "fa6a",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	dataa => d1_a1337_DATAA_driver,
	datab => d1_a1337_DATAB_driver,
	datac => d1_a1337_DATAC_driver,
	datad => d1_a1337_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => d1_a1337_combout);

d1_a1_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d1_a1_a_CLK_driver);

d1_a1_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(1),
	dataout => d1_a1_a_DATAA_driver);

d1_a1_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d1_a1_a_DATAB_driver);

d1_a1_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a1_a_DATAC_driver);

d1_a1_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1_a1337_combout,
	dataout => d1_a1_a_DATAD_driver);

d1_a1_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d1_a1_a_ACLR_driver);

d1_a1_a : cyclone_lcell
-- Equation(s):
-- d1(1) = DFFEAS(temp(0) & (Equal8_a71_combout & !temp(1) # !Equal8_a71_combout & (d1_a1337_combout)) # !temp(0) & (d1_a1337_combout), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "7f40",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d1_a1_a_CLK_driver,
	dataa => d1_a1_a_DATAA_driver,
	datab => d1_a1_a_DATAB_driver,
	datac => d1_a1_a_DATAC_driver,
	datad => d1_a1_a_DATAD_driver,
	aclr => d1_a1_a_ACLR_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d1(1));

Add1_a123_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(0),
	dataout => Add1_a123_DATAB_driver);

Add1_a123_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(2),
	dataout => Add1_a123_DATAC_driver);

Add1_a123_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(1),
	dataout => Add1_a123_DATAD_driver);

Add1_a123 : cyclone_lcell
-- Equation(s):
-- Add1_a123_combout = d1(2) $ (!d1(1) # !d1(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "c30f",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => Add1_a123_DATAB_driver,
	datac => Add1_a123_DATAC_driver,
	datad => Add1_a123_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Add1_a123_combout);

d1_a2_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d1_a2_a_CLK_driver);

d1_a2_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a62_combout,
	dataout => d1_a2_a_DATAA_driver);

d1_a2_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d1_a2_a_DATAB_driver);

d1_a2_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a2_a_DATAC_driver);

d1_a2_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Add1_a123_combout,
	dataout => d1_a2_a_DATAD_driver);

d1_a2_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d1_a2_a_ACLR_driver);

d1_a2_a_ENA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a2_a_ENA_driver);

d1_a2_a : cyclone_lcell
-- Equation(s):
-- d1(2) = DFFEAS(!temp(0) & !Add1_a123_combout & (!Equal8_a71_combout # !p2_a62_combout), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , Equal8_a71_combout, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0013",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d1_a2_a_CLK_driver,
	dataa => d1_a2_a_DATAA_driver,
	datab => d1_a2_a_DATAB_driver,
	datac => d1_a2_a_DATAC_driver,
	datad => d1_a2_a_DATAD_driver,
	aclr => d1_a2_a_ACLR_driver,
	ena => d1_a2_a_ENA_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => d1(2));

p2_a63_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(0),
	dataout => p2_a63_DATAB_driver);

p2_a63_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(2),
	dataout => p2_a63_DATAC_driver);

p2_a63_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(1),
	dataout => p2_a63_DATAD_driver);

p2_a63 : cyclone_lcell
-- Equation(s):
-- p2_a63_combout = d1(0) & !d1(2) & d1(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0c00",
	operation_mode => "normal",
	output_mode => "comb_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	datab => p2_a63_DATAB_driver,
	datac => p2_a63_DATAC_driver,
	datad => p2_a63_DATAD_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => p2_a63_combout);

d1_a3_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => hz_aregout,
	dataout => d1_a3_a_CLK_driver);

d1_a3_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => d1(3),
	dataout => d1_a3_a_DATAA_driver);

d1_a3_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => temp(0),
	dataout => d1_a3_a_DATAB_driver);

d1_a3_a_DATAC_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a3_a_DATAC_driver);

d1_a3_a_DATAD_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => p2_a63_combout,
	dataout => d1_a3_a_DATAD_driver);

d1_a3_a_ACLR_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => rst_acombout,
	dataout => d1_a3_a_ACLR_driver);

d1_a3_a_ENA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => Equal8_a71_combout,
	dataout => d1_a3_a_ENA_driver);

d1_a3_a : cyclone_lcell
-- Equation(s):
-- d1(3) = DFFEAS(!temp(0) & (d1(3) & (!p2_a63_combout) # !d1(3) & !Equal8_a71_combout & p2_a63_combout), GLOBAL(hz_aregout), !GLOBAL(rst_acombout), , Equal8_a71_combout, , , , )

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0122",
	operation_mode => "normal",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => d1_a3_a_CLK_driver,
	dataa => d1_a3_a_DATAA_driver,
	datab => d1_a3_a_DATAB_driver,
	datac => d1_a3_a_DATAC_driver,
	datad => d1_a3_a_DATAD_driver,
	aclr => d1_a3_a_ACLR_driver,