traffic.vho

vhdl实现的交通灯

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version"

-- DATE "03/19/2009 17:37:37"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	traffic IS
    PORT (
	rst : IN std_logic;
	clk : IN std_logic;
	ss : OUT std_logic_vector(5 DOWNTO 0);
	time1 : OUT std_logic_vector(3 DOWNTO 0);
	time2 : OUT std_logic_vector(3 DOWNTO 0)
	);
END traffic;

ARCHITECTURE structure OF traffic IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_ss : std_logic_vector(5 DOWNTO 0);
SIGNAL ww_time1 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_time2 : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_acombout : std_logic;
SIGNAL con_a0_a_a103 : std_logic;
SIGNAL con_a0_a_a103COUT1 : std_logic;
SIGNAL con_a1_a_a105 : std_logic;
SIGNAL con_a1_a_a105COUT1 : std_logic;
SIGNAL con_a2_a_a107 : std_logic;
SIGNAL con_a2_a_a107COUT1 : std_logic;
SIGNAL con_a3_a_a109 : std_logic;
SIGNAL con_a3_a_a109COUT1 : std_logic;
SIGNAL con_a4_a_a111 : std_logic;
SIGNAL con_a5_a_a113 : std_logic;
SIGNAL con_a5_a_a113COUT1 : std_logic;
SIGNAL con_a6_a_a117 : std_logic;
SIGNAL con_a6_a_a117COUT1 : std_logic;
SIGNAL con_a7_a_a119 : std_logic;
SIGNAL con_a7_a_a119COUT1 : std_logic;
SIGNAL con_a8_a_a115 : std_logic;
SIGNAL con_a8_a_a115COUT1 : std_logic;
SIGNAL hz_a122_combout : std_logic;
SIGNAL hz_a123_combout : std_logic;
SIGNAL hz_a124_combout : std_logic;
SIGNAL hz_aregout : std_logic;
SIGNAL rst_acombout : std_logic;
SIGNAL d1_a1337_combout : std_logic;
SIGNAL Add1_a123_combout : std_logic;
SIGNAL p2_a63_combout : std_logic;
SIGNAL p2_a62_combout : std_logic;
SIGNAL d2_a594_combout : std_logic;
SIGNAL d2_a597_combout : std_logic;
SIGNAL Equal8_a71_combout : std_logic;
SIGNAL state_control_a475_combout : std_logic;
SIGNAL ss_a31_combout : std_logic;
SIGNAL Mux0_a6_combout : std_logic;
SIGNAL ss_a32_combout : std_logic;
SIGNAL Mux1_a25_combout : std_logic;
SIGNAL con : std_logic_vector(9 DOWNTO 0);
SIGNAL d1 : std_logic_vector(3 DOWNTO 0);
SIGNAL d2 : std_logic_vector(3 DOWNTO 0);
SIGNAL state_control : std_logic_vector(1 DOWNTO 0);
SIGNAL temp : std_logic_vector(1 DOWNTO 0);
SIGNAL ALT_INV_state_control : std_logic_vector(1 DOWNTO 1);
SIGNAL ALT_INV_Mux0_a6_combout : std_logic;
SIGNAL ALT_INV_d1 : std_logic_vector(1 DOWNTO 0);
SIGNAL ALT_INV_d2 : std_logic_vector(3 DOWNTO 0);
SIGNAL con_a0_a_CLK_driver : std_logic;
SIGNAL con_a0_a_DATAB_driver : std_logic;
SIGNAL con_a1_a_CLK_driver : std_logic;
SIGNAL con_a1_a_DATAA_driver : std_logic;
SIGNAL con_a1_a_CIN0_driver : std_logic;
SIGNAL con_a1_a_CIN1_driver : std_logic;
SIGNAL con_a2_a_CLK_driver : std_logic;
SIGNAL con_a2_a_DATAA_driver : std_logic;
SIGNAL con_a2_a_CIN0_driver : std_logic;
SIGNAL con_a2_a_CIN1_driver : std_logic;
SIGNAL con_a3_a_CLK_driver : std_logic;
SIGNAL con_a3_a_DATAB_driver : std_logic;
SIGNAL con_a3_a_CIN0_driver : std_logic;
SIGNAL con_a3_a_CIN1_driver : std_logic;
SIGNAL con_a4_a_CLK_driver : std_logic;
SIGNAL con_a4_a_DATAB_driver : std_logic;
SIGNAL con_a4_a_CIN0_driver : std_logic;
SIGNAL con_a4_a_CIN1_driver : std_logic;
SIGNAL con_a5_a_CLK_driver : std_logic;
SIGNAL con_a5_a_DATAB_driver : std_logic;
SIGNAL con_a5_a_CIN_driver : std_logic;
SIGNAL con_a6_a_CLK_driver : std_logic;
SIGNAL con_a6_a_DATAA_driver : std_logic;
SIGNAL con_a6_a_CIN_driver : std_logic;
SIGNAL con_a6_a_CIN0_driver : std_logic;
SIGNAL con_a6_a_CIN1_driver : std_logic;
SIGNAL con_a7_a_CLK_driver : std_logic;
SIGNAL con_a7_a_DATAA_driver : std_logic;
SIGNAL con_a7_a_CIN_driver : std_logic;
SIGNAL con_a7_a_CIN0_driver : std_logic;
SIGNAL con_a7_a_CIN1_driver : std_logic;
SIGNAL con_a8_a_CLK_driver : std_logic;
SIGNAL con_a8_a_DATAB_driver : std_logic;
SIGNAL con_a8_a_CIN_driver : std_logic;
SIGNAL con_a8_a_CIN0_driver : std_logic;
SIGNAL con_a8_a_CIN1_driver : std_logic;
SIGNAL con_a9_a_CLK_driver : std_logic;
SIGNAL con_a9_a_DATAA_driver : std_logic;
SIGNAL con_a9_a_CIN_driver : std_logic;
SIGNAL con_a9_a_CIN0_driver : std_logic;
SIGNAL con_a9_a_CIN1_driver : std_logic;
SIGNAL hz_a122_DATAA_driver : std_logic;
SIGNAL hz_a122_DATAB_driver : std_logic;
SIGNAL hz_a122_DATAC_driver : std_logic;
SIGNAL hz_a122_DATAD_driver : std_logic;
SIGNAL hz_a123_DATAC_driver : std_logic;
SIGNAL hz_a123_DATAD_driver : std_logic;
SIGNAL hz_a124_DATAA_driver : std_logic;
SIGNAL hz_a124_DATAB_driver : std_logic;
SIGNAL hz_a124_DATAC_driver : std_logic;
SIGNAL hz_a124_DATAD_driver : std_logic;
SIGNAL hz_CLK_driver : std_logic;
SIGNAL hz_DATAA_driver : std_logic;
SIGNAL hz_DATAB_driver : std_logic;
SIGNAL hz_DATAC_driver : std_logic;
SIGNAL hz_DATAD_driver : std_logic;
SIGNAL temp_a1_a_CLK_driver : std_logic;
SIGNAL temp_a1_a_DATAC_driver : std_logic;
SIGNAL temp_a1_a_DATAD_driver : std_logic;
SIGNAL temp_a1_a_ACLR_driver : std_logic;
SIGNAL temp_a1_a_ENA_driver : std_logic;
SIGNAL d1_a0_a_CLK_driver : std_logic;
SIGNAL d1_a0_a_DATAA_driver : std_logic;
SIGNAL d1_a0_a_DATAB_driver : std_logic;
SIGNAL d1_a0_a_DATAC_driver : std_logic;
SIGNAL d1_a0_a_DATAD_driver : std_logic;
SIGNAL d1_a0_a_ACLR_driver : std_logic;
SIGNAL d1_a1337_DATAA_driver : std_logic;
SIGNAL d1_a1337_DATAB_driver : std_logic;
SIGNAL d1_a1337_DATAC_driver : std_logic;
SIGNAL d1_a1337_DATAD_driver : std_logic;
SIGNAL d1_a1_a_CLK_driver : std_logic;
SIGNAL d1_a1_a_DATAA_driver : std_logic;
SIGNAL d1_a1_a_DATAB_driver : std_logic;
SIGNAL d1_a1_a_DATAC_driver : std_logic;
SIGNAL d1_a1_a_DATAD_driver : std_logic;
SIGNAL d1_a1_a_ACLR_driver : std_logic;
SIGNAL Add1_a123_DATAB_driver : std_logic;
SIGNAL Add1_a123_DATAC_driver : std_logic;
SIGNAL Add1_a123_DATAD_driver : std_logic;
SIGNAL d1_a2_a_CLK_driver : std_logic;
SIGNAL d1_a2_a_DATAA_driver : std_logic;
SIGNAL d1_a2_a_DATAB_driver : std_logic;
SIGNAL d1_a2_a_DATAC_driver : std_logic;
SIGNAL d1_a2_a_DATAD_driver : std_logic;
SIGNAL d1_a2_a_ACLR_driver : std_logic;
SIGNAL d1_a2_a_ENA_driver : std_logic;
SIGNAL p2_a63_DATAB_driver : std_logic;
SIGNAL p2_a63_DATAC_driver : std_logic;
SIGNAL p2_a63_DATAD_driver : std_logic;
SIGNAL d1_a3_a_CLK_driver : std_logic;
SIGNAL d1_a3_a_DATAA_driver : std_logic;
SIGNAL d1_a3_a_DATAB_driver : std_logic;
SIGNAL d1_a3_a_DATAC_driver : std_logic;
SIGNAL d1_a3_a_DATAD_driver : std_logic;
SIGNAL d1_a3_a_ACLR_driver : std_logic;
SIGNAL d1_a3_a_ENA_driver : std_logic;
SIGNAL p2_a62_DATAA_driver : std_logic;
SIGNAL p2_a62_DATAB_driver : std_logic;
SIGNAL p2_a62_DATAC_driver : std_logic;
SIGNAL p2_a62_DATAD_driver : std_logic;
SIGNAL d2_a0_a_CLK_driver : std_logic;
SIGNAL d2_a0_a_DATAC_driver : std_logic;
SIGNAL d2_a0_a_ACLR_driver : std_logic;
SIGNAL d2_a594_DATAB_driver : std_logic;
SIGNAL d2_a594_DATAC_driver : std_logic;
SIGNAL d2_a594_DATAD_driver : std_logic;
SIGNAL d2_a1_a_CLK_driver : std_logic;
SIGNAL d2_a1_a_DATAA_driver : std_logic;
SIGNAL d2_a1_a_DATAB_driver : std_logic;
SIGNAL d2_a1_a_DATAC_driver : std_logic;
SIGNAL d2_a1_a_DATAD_driver : std_logic;
SIGNAL d2_a1_a_ACLR_driver : std_logic;
SIGNAL d2_a597_DATAA_driver : std_logic;
SIGNAL d2_a597_DATAB_driver : std_logic;
SIGNAL d2_a597_DATAC_driver : std_logic;
SIGNAL d2_a597_DATAD_driver : std_logic;
SIGNAL d2_a3_a_CLK_driver : std_logic;
SIGNAL d2_a3_a_DATAA_driver : std_logic;
SIGNAL d2_a3_a_DATAB_driver : std_logic;
SIGNAL d2_a3_a_DATAC_driver : std_logic;
SIGNAL d2_a3_a_DATAD_driver : std_logic;
SIGNAL d2_a3_a_ACLR_driver : std_logic;
SIGNAL d2_a2_a_CLK_driver : std_logic;
SIGNAL d2_a2_a_DATAA_driver : std_logic;
SIGNAL d2_a2_a_DATAB_driver : std_logic;
SIGNAL d2_a2_a_DATAC_driver : std_logic;
SIGNAL d2_a2_a_DATAD_driver : std_logic;
SIGNAL d2_a2_a_ACLR_driver : std_logic;
SIGNAL Equal8_a71_DATAA_driver : std_logic;
SIGNAL Equal8_a71_DATAB_driver : std_logic;
SIGNAL Equal8_a71_DATAC_driver : std_logic;
SIGNAL Equal8_a71_DATAD_driver : std_logic;
SIGNAL temp_a0_a_CLK_driver : std_logic;
SIGNAL temp_a0_a_DATAB_driver : std_logic;
SIGNAL temp_a0_a_DATAC_driver : std_logic;
SIGNAL temp_a0_a_DATAD_driver : std_logic;
SIGNAL temp_a0_a_ACLR_driver : std_logic;
SIGNAL state_control_a0_a_CLK_driver : std_logic;
SIGNAL state_control_a0_a_DATAA_driver : std_logic;
SIGNAL state_control_a0_a_DATAB_driver : std_logic;
SIGNAL state_control_a0_a_DATAC_driver : std_logic;
SIGNAL state_control_a0_a_DATAD_driver : std_logic;
SIGNAL state_control_a0_a_ACLR_driver : std_logic;
SIGNAL state_control_a475_DATAB_driver : std_logic;
SIGNAL state_control_a475_DATAC_driver : std_logic;
SIGNAL state_control_a475_DATAD_driver : std_logic;
SIGNAL state_control_a1_a_CLK_driver : std_logic;
SIGNAL state_control_a1_a_DATAA_driver : std_logic;
SIGNAL state_control_a1_a_DATAB_driver : std_logic;
SIGNAL state_control_a1_a_DATAD_driver : std_logic;
SIGNAL state_control_a1_a_ACLR_driver : std_logic;
SIGNAL ss_a31_DATAA_driver : std_logic;
SIGNAL ss_a31_DATAC_driver : std_logic;
SIGNAL ss_a31_DATAD_driver : std_logic;
SIGNAL Mux0_a6_DATAA_driver : std_logic;
SIGNAL Mux0_a6_DATAC_driver : std_logic;
SIGNAL ss_a32_DATAB_driver : std_logic;
SIGNAL ss_a32_DATAC_driver : std_logic;
SIGNAL ss_a32_DATAD_driver : std_logic;
SIGNAL Mux1_a25_DATAB_driver : std_logic;
SIGNAL Mux1_a25_DATAC_driver : std_logic;
SIGNAL ss_a0_a_DATAIN_driver : std_logic;
SIGNAL ss_a1_a_DATAIN_driver : std_logic;
SIGNAL ss_a2_a_DATAIN_driver : std_logic;
SIGNAL ss_a3_a_DATAIN_driver : std_logic;
SIGNAL ss_a4_a_DATAIN_driver : std_logic;
SIGNAL ss_a5_a_DATAIN_driver : std_logic;
SIGNAL time1_a0_a_DATAIN_driver : std_logic;
SIGNAL time1_a1_a_DATAIN_driver : std_logic;
SIGNAL time1_a2_a_DATAIN_driver : std_logic;
SIGNAL time1_a3_a_DATAIN_driver : std_logic;
SIGNAL time2_a0_a_DATAIN_driver : std_logic;
SIGNAL time2_a1_a_DATAIN_driver : std_logic;
SIGNAL time2_a2_a_DATAIN_driver : std_logic;
SIGNAL time2_a3_a_DATAIN_driver : std_logic;

BEGIN

ww_rst <= rst;
ww_clk <= clk;
ss <= ww_ss;
time1 <= ww_time1;
time2 <= ww_time2;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
ALT_INV_state_control(1) <= NOT state_control(1);
ALT_INV_Mux0_a6_combout <= NOT Mux0_a6_combout;
ALT_INV_d1(0) <= NOT d1(0);
ALT_INV_d1(1) <= NOT d1(1);
ALT_INV_d2(0) <= NOT d2(0);
ALT_INV_d2(3) <= NOT d2(3);

clk_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => clk_acombout);

con_a0_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => clk_acombout,
	dataout => con_a0_a_CLK_driver);

con_a0_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con(0),
	dataout => con_a0_a_DATAB_driver);

con_a0_a : cyclone_lcell
-- Equation(s):
-- con(0) = DFFEAS(!con(0), GLOBAL(clk_acombout), VCC, , , , , , )
-- con_a0_a_a103 = CARRY(con(0))
-- con_a0_a_a103COUT1 = CARRY(con(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "33cc",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => con_a0_a_CLK_driver,
	datab => con_a0_a_DATAB_driver,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => con(0),
	cout0 => con_a0_a_a103,
	cout1 => con_a0_a_a103COUT1);

con_a1_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => clk_acombout,
	dataout => con_a1_a_CLK_driver);

con_a1_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con(1),
	dataout => con_a1_a_DATAA_driver);

con_a1_a_CIN0_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con_a0_a_a103,
	dataout => con_a1_a_CIN0_driver);

con_a1_a_CIN1_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con_a0_a_a103COUT1,
	dataout => con_a1_a_CIN1_driver);

con_a1_a : cyclone_lcell
-- Equation(s):
-- con(1) = DFFEAS(con(1) $ (con_a0_a_a103), GLOBAL(clk_acombout), VCC, , , , , , )
-- con_a1_a_a105 = CARRY(!con_a0_a_a103 # !con(1))
-- con_a1_a_a105COUT1 = CARRY(!con_a0_a_a103COUT1 # !con(1))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "5a5f",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => con_a1_a_CLK_driver,
	dataa => con_a1_a_DATAA_driver,
	aclr => GND,
	cin0 => con_a1_a_CIN0_driver,
	cin1 => con_a1_a_CIN1_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => con(1),
	cout0 => con_a1_a_a105,
	cout1 => con_a1_a_a105COUT1);

con_a2_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => clk_acombout,
	dataout => con_a2_a_CLK_driver);

con_a2_a_DATAA_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con(2),
	dataout => con_a2_a_DATAA_driver);

con_a2_a_CIN0_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con_a1_a_a105,
	dataout => con_a2_a_CIN0_driver);

con_a2_a_CIN1_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con_a1_a_a105COUT1,
	dataout => con_a2_a_CIN1_driver);

con_a2_a : cyclone_lcell
-- Equation(s):
-- con(2) = DFFEAS(con(2) $ (!con_a1_a_a105), GLOBAL(clk_acombout), VCC, , , , , , )
-- con_a2_a_a107 = CARRY(con(2) & (!con_a1_a_a105))
-- con_a2_a_a107COUT1 = CARRY(con(2) & (!con_a1_a_a105COUT1))

-- pragma translate_off
GENERIC MAP (
	cin0_used => "true",
	cin1_used => "true",
	lut_mask => "a50a",
	operation_mode => "arithmetic",
	output_mode => "reg_only",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	clk => con_a2_a_CLK_driver,
	dataa => con_a2_a_DATAA_driver,
	aclr => GND,
	cin0 => con_a2_a_CIN0_driver,
	cin1 => con_a2_a_CIN1_driver,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => con(2),
	cout0 => con_a2_a_a107,
	cout1 => con_a2_a_a107COUT1);

con_a3_a_CLK_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => clk_acombout,
	dataout => con_a3_a_CLK_driver);

con_a3_a_DATAB_routing_wire_inst : cyclone_routing_wire
PORT MAP (
	datain => con(3),
	dataout => con_a3_a_DATAB_driver);