mile.v

密勒码最初用于气象卫星和磁记录

// Company: 
// Engineer: 
// 
// Create Date:    11:23:21 10/28/2008 
// Design Name: 
// Module Name:    MILE - Behavioral 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 


`timescale 1ns/1ps

 module MILE (
		//input 
		DIN, 
		CLK,
		RESET,
		//output
		DOUT,
		DATA_EN,
		BIT_EN
		);
		
input  DIN,CLK,RESET;
output DOUT,DATA_EN,BIT_EN;

//define receiver state
`define A 2'b00
`define B 2'b01
`define C 2'b10
`define compare 2'b11

//define frame state
`define idle 2'b00
`define start 2'b01
`define data 2'b10

reg DOUT,DATA_EN;
wire BIT_EN;
reg Detect_A,Detect_B,Detect_C;
wire BIT_EN_temp;

//parameter A=2'b00, B=2'b01, C=2'b10, compare=2'b11;  //define receiver state
//parameter idle = 2'b00, start = 2'b01, data = 2'b10;	//define frame state

reg[1:0] current_state,next_state;		  //state machine register of detect signal
reg[1:0] decode_state,decode_next_state,decode_last_state;	//	state machine register of decode


reg[4:0] count;       //counter the 'one' number

assign BIT_EN_temp = Detect_A | Detect_B | Detect_C;	//Bit enable temp
assign BIT_EN = BIT_EN_temp & DATA_EN;	//Bit enable output

// ouput detected Detect & BIT_EN flag
always @(posedge CLK or negedge RESET)
begin
	if(!RESET)
		begin
			Detect_A<= 1'b0; 
			Detect_B<= 1'b0; 
			Detect_C<= 1'b0;
		end
	else
		begin
		if (current_state ==`A && count ==5'd9)
			begin
    		Detect_A<= 1'b1; 
			Detect_B<= 1'b0; 
			Detect_C<= 1'b0;
			end
  		else if ( current_state ==`B && count ==5'd13) 
    		begin
    		Detect_A<= 1'b0; 
			Detect_B<= 1'b1; 
			Detect_C<= 1'b0;
			end
		else if (current_state ==`C && count ==5'd9)
			begin
    		Detect_A<= 1'b0; 
			Detect_B<= 1'b0; 
			Detect_C<= 1'b1;
			end
		else
			begin
    		Detect_A<= 1'b0; 
			Detect_B<= 1'b0; 
			Detect_C<= 1'b0;
			end
	end
end

//counter the 'one' bit 
always @(negedge RESET or posedge CLK)
begin
	if (!RESET)
		count  <= 5'h0; 
	else  
    	begin
		if (count == 5'd16 && current_state==`B)
			count<=5'b1;
		else if(count == 5'd11 && (current_state==`C || current_state==`A))
			count <=5'h1;
		else
		   	count <= count +1;    
    end 
end

always @(posedge CLK or negedge RESET)  
begin
	if (!RESET)
      	current_state <= `B; 		//idle
	else
		current_state <= next_state;
end

//FSM of receive input  
always @(current_state or DIN or count)//current_state or count or DIN)
begin
	case(current_state)
		`B:	begin
			if(DIN==0)
			begin
				if(count==5'd16)
					next_state <= `C;
				else if(count==5'd8)
					next_state <= `A;
				else
					next_state <= `B;
			end
			else
				next_state <= `B;		
		end
		`A:	begin
			if(DIN==0)
			begin
				if(count==5'd11)
					next_state <= `C;
				else if(count==5'd8 || count==5'd13)
					next_state <= `A;
			end
			else 
			begin
				if(count==5'd11)
					next_state <= `compare;
				else
					next_state <= `A;
			end	
		end
		`C:	begin
			if(DIN==0)
				next_state <= `C;
			else
			begin
				if(count==5'd11)	
					next_state <= `compare;
				else
					next_state <= `C;
			end	
		end
		`compare:	begin
			if(DIN==0)
				next_state <= `A;
			else if(count==5'd9)
				next_state <= `B;
			else
				next_state <= `compare;
		end
		default: next_state <= current_state;
	endcase
end


//save the last signal 
reg [1:0] last_detect,current_detect;
always @(posedge CLK or negedge RESET)
begin
	if(!RESET)
		begin
		last_detect <= `B;
		current_detect <= `B;
		end
	else if(Detect_A==1)	
		begin
		last_detect <= current_detect;
		current_detect <= `A;
		end
	else if(Detect_B==1)	
		begin
		last_detect <= current_detect;
		current_detect <= `B;
		end	
	else if(Detect_C==1)
		begin
		last_detect <= current_detect;
		current_detect <= `C;
		end
	else
		begin
		last_detect <= last_detect;
		current_detect <= current_detect;
		end
end

always @(posedge CLK or negedge RESET)  
begin
	if (!RESET)
		begin
      	decode_state <= `idle; 		//idle
      	decode_last_state <= `idle;
		end
	else
		begin
		decode_last_state <= decode_state;
		decode_state <= decode_next_state;
		end
end

//fsm of decode
always @(decode_state or current_detect or last_detect) //FSM of decode
begin
	case(decode_state)
		`idle:
			begin
			if(current_detect==`C)	//detect start code
				decode_next_state <= `start;
			else
				decode_next_state <= `idle;
			end
		`start:
			begin					//next 	
			if(last_detect==`C && current_detect==`C)	
				decode_next_state <= `data;
			else if((last_detect!=`C && current_detect==`C) || (last_detect==`C && current_detect!=`C))
				decode_next_state <= `start;
			else
				decode_next_state <= `data;
			end
		`data:
			begin
			if(current_detect==`B && (last_detect==`B || last_detect==`C))	//detect finish code
				decode_next_state <= `idle;
			else
				decode_next_state <= `data;	//continue data
			end
		default:
			decode_next_state <= `idle;
	endcase
end


// output 
always @(decode_state or last_detect or current_detect or decode_last_state)
begin
	case(decode_state)
		`idle:
			begin
			DATA_EN <= 0;
			DOUT <= 0;
			end
		`start:
			begin
			DATA_EN <= 0;
			DOUT <= 0;
			end
        `data:
			begin
			case ({last_detect,current_detect})
				{`A,`A}: 
					begin 
					DOUT <= 1; 
					DATA_EN<=1; 
					end
				{`A,`B}: 
					begin 
					DOUT <= 1; 
					DATA_EN<=1; 
					end
				{`B,`A}: 
					begin 
					DOUT <= 0; 
					DATA_EN<=1; 
					end
				{`B,`C}: 
					begin 
					DOUT <= 0; 
					DATA_EN<=1; 
					end
				{`C,`A}: 
					begin 
					DOUT <= 0;
					DATA_EN<=1; 
					end
				{`C,`C}:
					begin
					DOUT <= 0;
					if(decode_last_state==`start)
				        DATA_EN <= 0;
					else
						DATA_EN <= 1;
				    end
			endcase
			end
		default:
			begin
				DATA_EN<=0;
				DOUT<=0;
			end
	endcase
end  



endmodule