mile_tb.v

来自「密勒码最初用于气象卫星和磁记录」· Verilog 代码 · 共 150 行

`timescale 1ns/1ps
module MILE_tb  ; 

  wire    DATA_EN   ; 
  wire    DOUT   ; 
  wire    BIT_EN   ; 
  reg    CLK   ; 
  reg    RESET   ; 
  reg    DIN   ; 
  MILE 
   DUT  ( 
       .DATA_EN (DATA_EN ) ,
      .DOUT (DOUT ) ,
      .BIT_EN (BIT_EN ) ,
      .CLK (CLK ) ,
      .RESET (RESET ) ,
      .DIN (DIN ) ); 
      

reg clock;
initial	//RESET 
begin
   RESET = 0;
   #20  RESET = 1;  // 1 clock period
end

initial // Clock generator
  begin
    clock= 0;
    #0 forever #10 clock= !clock;
  end  


initial	// Test stimulus
  begin
    DIN=1;
    #20  DIN=1;  //RESET
    // ONE FRAME:10010110 
    //frame1={C,A,B,C,A,B,A,A,B,C,B};
    #320 DIN=0;		//B idle
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=0;		//B
    #110 DIN=1;		//C
    #210 DIN=1; 
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=0;		//B
    #110 DIN=1;		//C
    #210 DIN=1; 
    #320 DIN=1;		//B
    
    //second frame:00010100
    //frame2={C,C,C,C,A,B,A,B,C,C,B};
    #320 DIN=0;		//B idle
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=0;		//B
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=1;
    #320 DIN=1;		//B
    
    //third frame:10100101
    //frame3={C,A,B,A,B,C,A,B,A,B,B};
    #320 DIN=0;		//B idle
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=0;		//B
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #320 DIN=1;		//B
    
    //Fourth frame:00100111
    //frame4={C,C,C,A,B,C,A,A,A,B,B};
    #320 DIN=0;		//B idle
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=0;
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=0;		//B
    #110 DIN=1;		//C
    #210 DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #160 DIN=0;		//A
    #110 DIN=1;		
    #50  DIN=1;
    #320 DIN=1;		//B
    #320 DIN=1;		//B
    end 
// generate system clk
always @ (clock) //din clock
begin
  CLK = DIN & clock;  
end


endmodule