vga_800_600.tan.rpt

来自「VGA彩色信号控制器设计：用VHDL语言编写程序」· RPT 代码 · 共 288 行 · 第 1/5 页

; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                                            ; To                    ;
+------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------+-----------------------+
; Worst-case tsu         ; N/A   ; None          ; 9.100 ns                         ; s[0]                                                            ; vga_800_600:u1|g~reg0 ;
; Worst-case tco         ; N/A   ; None          ; 13.600 ns                        ; vga_800_600:u1|vs~reg0                                          ; vs_out                ;
; Worst-case th          ; N/A   ; None          ; -1.100 ns                        ; s[1]                                                            ; vga_800_600:u1|b~reg0 ;
; Worst-case minimum tco ; N/A   ; None          ; 10.100 ns                        ; vga_800_600:u1|hs~reg0                                          ; hs_out                ;
; Clock Setup: 'clk_50M' ; N/A   ; None          ; 19.76 MHz ( period = 50.600 ns ) ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q10[1]        ;
+------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------+-----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk_50M         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_50M'                                                                                                                                                                                                                                                                              ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                            ; To             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-----------------------------------------------------------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 19.76 MHz ( period = 50.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q10[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 19.92 MHz ( period = 50.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q10[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.08 MHz ( period = 49.800 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[6] ; move:u5|q10[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.24 MHz ( period = 49.400 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[7] ; move:u5|q10[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q4[0]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[8] ; move:u5|q10[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.41 MHz ( period = 49.000 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q4[1]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.49 MHz ( period = 48.800 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q11[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.58 MHz ( period = 48.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q12[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.58 MHz ( period = 48.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q14[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.58 MHz ( period = 48.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q4[0]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.58 MHz ( period = 48.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q14[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.58 MHz ( period = 48.600 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q4[1]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.66 MHz ( period = 48.400 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q13[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.66 MHz ( period = 48.400 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q11[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.66 MHz ( period = 48.400 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q13[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q12[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q14[0] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q7[0]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[6] ; move:u5|q4[0]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[4] ; move:u5|q5[0]  ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;
; N/A                                     ; 20.75 MHz ( period = 48.200 ns )                           ; move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter|q[5] ; move:u5|q14[1] ; clk_50M    ; clk_50M  ; None                        ; None                      ; None                    ;