vga_800_600.map.rpt

来自「VGA彩色信号控制器设计：用VHDL语言编写程序」· RPT 代码 · 共 393 行 · 第 1/2 页

;          |addcore:adder|                  ; 7 (1)       ; 0         ; 0           ; 0    ; 7 (1)        ; 0 (0)             ; 0 (0)            ; 7 (1)           ; |img|move:u5|lpm_add_sub:i_rtl_8|addcore:adder                            ;
;             |a_csnbuffer:result_node|     ; 6 (6)       ; 0         ; 0           ; 0    ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 6 (6)           ; |img|move:u5|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node    ;
;       |lpm_add_sub:i_rtl_9|               ; 9 (0)       ; 0         ; 0           ; 0    ; 9 (0)        ; 0 (0)             ; 0 (0)            ; 9 (0)           ; |img|move:u5|lpm_add_sub:i_rtl_9                                          ;
;          |addcore:adder|                  ; 9 (1)       ; 0         ; 0           ; 0    ; 9 (1)        ; 0 (0)             ; 0 (0)            ; 9 (1)           ; |img|move:u5|lpm_add_sub:i_rtl_9|addcore:adder                            ;
;             |a_csnbuffer:result_node|     ; 8 (8)       ; 0         ; 0           ; 0    ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 8 (8)           ; |img|move:u5|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node    ;
;       |lpm_counter:a_rtl_4|               ; 7 (0)       ; 7         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 7 (0)            ; 7 (0)           ; |img|move:u5|lpm_counter:a_rtl_4                                          ;
;          |alt_counter_f10ke:wysi_counter| ; 7 (7)       ; 7         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 7 (7)           ; |img|move:u5|lpm_counter:a_rtl_4|alt_counter_f10ke:wysi_counter           ;
;       |lpm_counter:cnt_rtl_2|             ; 6 (0)       ; 6         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 6 (0)            ; 6 (0)           ; |img|move:u5|lpm_counter:cnt_rtl_2                                        ;
;          |alt_counter_f10ke:wysi_counter| ; 6 (6)       ; 6         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |img|move:u5|lpm_counter:cnt_rtl_2|alt_counter_f10ke:wysi_counter         ;
;    |number:u4|                            ; 67 (58)     ; 23        ; 0           ; 0    ; 44 (44)      ; 0 (0)             ; 23 (14)          ; 9 (0)           ; |img|number:u4                                                            ;
;       |lpm_counter:cc_rtl_5|              ; 5 (0)       ; 5         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 5 (0)           ; |img|number:u4|lpm_counter:cc_rtl_5                                       ;
;          |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 5         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 5 (5)           ; |img|number:u4|lpm_counter:cc_rtl_5|alt_counter_f10ke:wysi_counter        ;
;       |lpm_counter:cnt_rtl_3|             ; 4 (0)       ; 4         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |img|number:u4|lpm_counter:cnt_rtl_3                                      ;
;          |alt_counter_f10ke:wysi_counter| ; 4 (4)       ; 4         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |img|number:u4|lpm_counter:cnt_rtl_3|alt_counter_f10ke:wysi_counter       ;
;    |vga_800_600:u1|                       ; 44 (19)     ; 25        ; 0           ; 0    ; 19 (14)      ; 1 (1)             ; 24 (4)           ; 20 (0)          ; |img|vga_800_600:u1                                                       ;
;       |lpm_counter:hcnt_rtl_0|            ; 11 (0)      ; 10        ; 0           ; 0    ; 1 (0)        ; 0 (0)             ; 10 (0)           ; 10 (0)          ; |img|vga_800_600:u1|lpm_counter:hcnt_rtl_0                                ;
;          |alt_counter_f10ke:wysi_counter| ; 11 (11)     ; 10        ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |img|vga_800_600:u1|lpm_counter:hcnt_rtl_0|alt_counter_f10ke:wysi_counter ;
;       |lpm_counter:vcnt_rtl_1|            ; 14 (0)      ; 10        ; 0           ; 0    ; 4 (0)        ; 0 (0)             ; 10 (0)           ; 10 (0)          ; |img|vga_800_600:u1|lpm_counter:vcnt_rtl_1                                ;
;          |alt_counter_f10ke:wysi_counter| ; 14 (14)     ; 10        ; 0           ; 0    ; 4 (4)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |img|vga_800_600:u1|lpm_counter:vcnt_rtl_1|alt_counter_f10ke:wysi_counter ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in C:/Documents and Settings/刘峰　/桌面/vga/vga_800_600/vga_800_600.map.eqn.


+-----------------------------------------------------------------+
; Analysis & Synthesis Files Read                                 ;
+------------------------------------------------------------------
; File Name                                                ; Read ;
+----------------------------------------------------------+------+
; choose.vhd                                               ; Read ;
; vga_800_600.vhd                                          ; Read ;
; gepan.vhd                                                ; Read ;
; img.vhd                                                  ; Read ;
; number.vhd                                               ; Read ;
; move.vhd                                                 ; Read ;
; f:/quartus/libraries/megafunctions/lpm_counter.tdf       ; Read ;
; f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ; Read ;
; f:/quartus/libraries/megafunctions/lpm_add_sub.tdf       ; Read ;
; f:/quartus/libraries/megafunctions/addcore.tdf           ; Read ;
; f:/quartus/libraries/megafunctions/a_csnbuffer.tdf       ; Read ;
; f:/quartus/libraries/megafunctions/altshift.tdf          ; Read ;
+----------------------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource                      ; Usage       ;
+-------------------------------+-------------+
; Logic cells                   ; 480         ;
; Total combinational functions ; 477         ;
; Total registers               ; 118         ;
; I/O pins                      ; 9           ;
; Maximum fan-out node          ; clk_50M     ;
; Maximum fan-out               ; 93          ;
; Total fan-out                 ; 1737        ;
; Average fan-out               ; 3.55        ;
+-------------------------------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 42    ;
; Number of synthesis-generated cells                    ; 438   ;
; Number of WYSIWYG LUTs                                 ; 42    ;
; Number of synthesis-generated LUTs                     ; 435   ;
; Number of WYSIWYG registers                            ; 42    ;
; Number of synthesis-generated registers                ; 76    ;
; Number of cells with combinational logic only          ; 362   ;
; Number of cells with registers only                    ; 3     ;
; Number of cells with combinational logic and registers ; 115   ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 32    ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 0     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 10    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Dec 10 14:02:44 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off vga_800_600 -c vga_800_600
Info: Found 2 design units and 1 entities in source file choose.vhd
    Info: Found design unit 1: choose-abc
    Info: Found entity 1: choose
Info: Found 2 design units and 1 entities in source file vga_800_600.vhd
    Info: Found design unit 1: vga_800_600-one
    Info: Found entity 1: vga_800_600
Info: Found 2 design units and 1 entities in source file gepan.vhd
    Info: Found design unit 1: gepan-one
    Info: Found entity 1: gepan
Info: Found 2 design units and 1 entities in source file img.vhd
    Info: Found design unit 1: img-vhd
    Info: Found entity 1: img
Info: Found 2 design units and 1 entities in source file number.vhd
    Info: Found design unit 1: number-one
    Info: Found entity 1: number
Info: Found 2 design units and 1 entities in source file move.vhd
    Info: Found design unit 1: move-one
    Info: Found entity 1: move
Info: VHDL Case Statement information at number.vhd(53): OTHERS choice is never selected
Warning: Reduced output of register q1[0] with stuck data_in to GND at number.vhd(68)
Warning: Reduced output of register q2[1] with stuck data_in to GND at number.vhd(77)
Warning: Reduced output of register q3[1] with stuck data_in to GND at number.vhd(86)
Warning: Reduced output of register q3[0] with stuck data_in to GND at number.vhd(86)
Warning: Reduced output of register q4[2] with stuck data_in to GND at number.vhd(95)
Warning: Reduced output of register q5[2] with stuck data_in to GND at number.vhd(104)
Warning: Reduced output of register q5[0] with stuck data_in to GND at number.vhd(104)
Warning: Reduced output of register q6[2] with stuck data_in to GND at number.vhd(113)
Warning: Reduced output of register q6[1] with stuck data_in to GND at number.vhd(113)
Warning: Reduced output of register q8[0] with stuck data_in to GND at number.vhd(131)
Warning: Reduced output of register q9[1] with stuck data_in to GND at number.vhd(140)
Info: VHDL Case Statement information at move.vhd(510): OTHERS choice is never selected
Warning: Reduced output of register q0[2] with stuck data_in to VCC at move.vhd(37)
Warning: Reduced output of register q0[1] with stuck data_in to VCC at move.vhd(37)
Warning: Reduced output of register q0[0] with stuck data_in to VCC at move.vhd(37)
Warning: Reduced output of register q3[2] with stuck data_in to VCC at move.vhd(64)
Warning: Reduced output of register q14[2] with stuck data_in to GND at move.vhd(214)
Warning: Reduced output of register q15[2] with stuck data_in to GND at move.vhd(228)
Warning: Reduced output of register q16[2] with stuck data_in to GND at move.vhd(242)
Warning: Reduced output of register q16[1] with stuck data_in to GND at move.vhd(242)
Warning: Reduced output of register q17[2] with stuck data_in to GND at move.vhd(257)
Warning: Reduced output of register q17[1] with stuck data_in to GND at move.vhd(257)
Warning: Reduced output of register q18[2] with stuck data_in to VCC at move.vhd(273)
Warning: Reduced output of register q18[1] with stuck data_in to VCC at move.vhd(273)
Warning: Reduced output of register q18[0] with stuck data_in to VCC at move.vhd(273)
Warning: Reduced output of register q21[2] with stuck data_in to VCC at move.vhd(300)
Warning: Reduced output of register q28[0] with stuck data_in to GND at move.vhd(396)
Warning: Reduced output of register q32[2] with stuck data_in to GND at move.vhd(454)
Warning: Reduced output of register q32[0] with stuck data_in to GND at move.vhd(454)
Warning: Reduced register move:u5|a[1] with stuck data_in port to stuck value GND
Warning: Reduced register move:u5|a[0] with stuck data_in port to stuck value GND
Info: Inferred 6 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: vga_800_600:u1|hcnt[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: vga_800_600:u1|vcnt[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: move:u5|cnt[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: number:u4|cnt[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=7) from the following logic: move:u5|a[2]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: number:u4|cc[0]~0
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file f:/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register move:u5|q22[2] merged to single register move:u5|q4[2]
    Info: Duplicate register gepan:u3|q_x[2] merged to single register move:u5|q5[2]
    Info: Duplicate register move:u5|q1[2] merged to single register move:u5|q19[2]
    Info: Duplicate register move:u5|q20[2] merged to single register move:u5|q2[2]
    Info: Duplicate register move:u5|q31[2] merged to single register move:u5|q30[2]
    Info: Duplicate register move:u5|q29[1] merged to single register move:u5|q28[2]
    Info: Duplicate register move:u5|q22[1] merged to single register move:u5|q4[1]
    Info: Duplicate register gepan:u3|q_x[1] merged to single register move:u5|q7[1]
    Info: Duplicate register gepan:u3|q_x[0] merged to single register move:u5|q8[0]
    Info: Duplicate register move:u5|q2[0] merged to single register move:u5|q20[0]
    Info: Duplicate register move:u5|q22[0] merged to single register move:u5|q4[0]
    Info: Duplicate register move:u5|q19[0] merged to single register move:u5|q1[0]
Info: Implemented 489 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 5 output pins
    Info: Implemented 480 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Processing ended: Sat Dec 10 14:02:58 2005
    Info: Elapsed time: 00:00:14