choose.vhd

来自「VGA彩色信号控制器设计：用VHDL语言编写程序」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choose is
 port(s : in std_logic_vector(1 downto 0);
      a,b,c : in std_logic_vector(2 downto 0);
      qout : out std_logic_vector(2 downto 0));
end entity choose;
architecture abc of choose is
begin
process(s,a,b,c)
variable q1 : std_logic_vector(2 downto 0);
begin
qout<=q1;
case s is
when "00"=>q1:=a;
when "01"=>q1:=b;
when "10"=>q1:=c;
--when "11"=>q1:=d;
when others=>null;
end case;
end process;
end architecture abc;