vga_800_600.map.eqn

VGA彩色信号控制器设计：用VHDL语言编写程序

--F1L63 is move:u5|i550~55
--operation mode is normal

F1L63 = F1L191 & F1L7;


--F1L13 is move:u5|i475~231
--operation mode is normal

F1L13 = D1L53 # F1L04 & !F1L7;


--F1_i449 is move:u5|i449
--operation mode is normal

F1_i449 = F1L191 & F1_i314;


--F1L51 is move:u5|i262~30
--operation mode is normal

F1L51 = D1L5 & (D1L04 # F1L04 & !F1L091);


--F1L52 is move:u5|i431~72
--operation mode is normal

F1L52 = F1_i90 # !F1L191;


--F1L43 is move:u5|i515~32
--operation mode is normal

F1L43 = F1L191 & D1L53;


--E1L63 is number:u4|i~1192
--operation mode is normal

E1L63 = !H2_q[2] & !H2_q[3] # !H2_q[4];


--E1L73 is number:u4|i~1193
--operation mode is normal

E1L73 = !H2_q[9] & (E1L63 # !F1L641 # !H2_q[8]);


--E1L4 is number:u4|i55~71
--operation mode is normal

E1L4 = E1L3 & !H2_q[2] # !H2_q[5] # !H2_q[6];


--E1L6 is number:u4|i56~77
--operation mode is normal

E1L6 = D1L73 & E1L73 & (!E1L4 # !D1L02);


--D1L71 is gepan:u3|i~529
--operation mode is normal

D1L71 = D1L52 & !H2_q[8];


--E1L12 is number:u4|i~417
--operation mode is normal

E1L12 = !H1_q[9] & (F1L341 & H1L62 # !E1L33);


--D1L14 is gepan:u3|i~2289
--operation mode is normal

D1L14 = !H1_q[8] & (H1L62 # !H1_q[6] # !H1_q[7]);


--E1L2 is number:u4|i33~19
--operation mode is normal

E1L2 = rset & (!E1L43 # !H4_q[0]);


--E1_full is number:u4|full
--operation mode is normal

E1_full_lut_out = !H3_q[0] & !E1L44 & H3_q[4] & H3_q[3];
E1_full = DFFEA(E1_full_lut_out, !B1L91Q, , , , , );


--E1L83 is number:u4|i~1194
--operation mode is normal

E1L83 = D1L22 & !H2_q[6] # !H2_q[8];


--E1L93 is number:u4|i~1195
--operation mode is normal

E1L93 = !H2_q[7] & !H2_q[3];


--E1L04 is number:u4|i~1196
--operation mode is normal

E1L04 = E1L83 # B1L71 & E1L23 & E1L93;


--E1L61 is number:u4|i201~121
--operation mode is normal

E1L61 = E1L04 & !H2_q[9] & (H2_q[8] # !D1L52);


--E1L8 is number:u4|i105~133
--operation mode is normal

E1L8 = E1L6 & !D1L14 & (!E1L61 # !E1L12);


--E1L14 is number:u4|i~1197
--operation mode is normal

E1L14 = H1_q[5] & H1_q[7] & H1_q[6];


--E1L24 is number:u4|i~1198
--operation mode is normal

E1L24 = !H1_q[8] & (F1L18 # !E1L14);


--E1L81 is number:u4|i233~97
--operation mode is normal

E1L81 = !E1L24 & !H1_q[9] & (!E1L33 # !F1L531);


--E1L34 is number:u4|i~1199
--operation mode is normal

E1L34 = !H2_q[7] & (F1L931 & !B1L61 # !H2_q[6]);


--E1L01 is number:u4|i114~96
--operation mode is normal

E1L01 = H2_q[8] & !H2_q[9] & !D1L3 & !E1L34;


--E1L7 is number:u4|i65~53
--operation mode is normal

E1L7 = E1L24 # H2_q[8] & D1L3;


--E1_i56 is number:u4|i56
--operation mode is normal

E1_i56 = D1L14 # !E1L6;


--E1_i145 is number:u4|i145
--operation mode is normal

E1_i145 = D1L14 # !E1L01 # !E1L12;


--E1L9 is number:u4|i105~134
--operation mode is normal

E1L9 = E1L12 & E1L61;


--E1L21 is number:u4|i145~79
--operation mode is normal

E1L21 = E1L12 & E1L01;


--E1_i242 is number:u4|i242
--operation mode is normal

E1_i242 = !H1_q[8] & (F1L18 # !E1L14) # !E1L21;


--D1L24 is gepan:u3|i~2290
--operation mode is normal

D1L24 = !H1_q[4] & (!H1_q[2] # !H1_q[3]) # !H1_q[5];


--D1L34 is gepan:u3|i~2291
--operation mode is normal

D1L34 = !H1_q[9] & (B1L21 & D1L24 # !H1_q[8]);


--D1L44 is gepan:u3|i~2292
--operation mode is normal

D1L44 = D1L43 & !H1_q[9] & !H1_q[8];


--D1L21 is gepan:u3|i~53
--operation mode is normal

D1L21 = D1L11 & !H1_q[9];


--F1L741 is move:u5|i~7042
--operation mode is normal

F1L741 = H5_q[1] # H5_q[0] # H5_q[3] # !H5_q[2];


--F1L97 is move:u5|i~0
--operation mode is normal

F1L97 = F1L741 # H5_q[4] # !H5_q[5] # !H5_q[6];


--K2_unreg_res_node[8] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|unreg_res_node[8]
--operation mode is normal

K2_unreg_res_node[8] = M6_cout[7] $ H2_q[9];


--F1_q32[1] is move:u5|q32[1]
--operation mode is normal

F1_q32[1]_lut_out = F1L87 # F1L84 # F1L56 # !F1L55;
F1_q32[1] = DFFEA(F1_q32[1]_lut_out, clk_50M, , , , , );


--C1L4 is choose:u2|q1[1]~445
--operation mode is normal

C1L4 = H6_q[5] & F1_q32[1];


--C1L5 is choose:u2|q1[1]~446
--operation mode is normal

C1L5 = s[0] & C1L6 # !s[0] & !C1L4 # !s[1];


--D1L64Q is gepan:u3|q[1]~reg0
--operation mode is normal

D1L64Q_lut_out = F1_q7[1] & (D1_q_y[1] # D1_cnt) # !F1_q7[1] & D1_q_y[1] & !D1_cnt;
D1L64Q = DFFEA(D1L64Q_lut_out, clk_50M, , , , , );


--E1L76Q is number:u4|q[1]~reg0
--operation mode is normal

E1L76Q_lut_out = E1L54 # E1L52 & !H4_q[3] & !H4_q[1];
E1L76Q = DFFEA(E1L76Q_lut_out, clk_50M, , , , , );


--C1L7 is choose:u2|q1[1]~451
--operation mode is normal

C1L7 = (s[1] # s[0] & !E1L76Q # !s[0] & !D1L64Q) & CASCADE(C1L5);


--K5_unreg_res_node[7] is move:u5|lpm_add_sub:i_rtl_10|addcore:adder|unreg_res_node[7]
--operation mode is normal

K5_unreg_res_node[7] = M51_cout[6] $ H2_q[9];


--K4_unreg_res_node[8] is move:u5|lpm_add_sub:i_rtl_9|addcore:adder|unreg_res_node[8]
--operation mode is normal

K4_unreg_res_node[8] = M21_cout[7] $ H2_q[9];


--E1L31 is number:u4|i179~162
--operation mode is normal

E1L31 = E1L34 # D1L14 # !E1L73 # !H2_q[8];


--E1L41 is number:u4|i179~163
--operation mode is normal

E1L41 = E1L31 & (E1L24 # !E1L04);


--D1L8 is gepan:u3|i57~616
--operation mode is normal

D1L8 = !H1_q[3] # !H1_q[4] # !H1_q[2] # !H1_q[5];


--D1L9 is gepan:u3|i57~617
--operation mode is normal

D1L9 = !H1_q[8] & (D1L8 & !H1_q[6] # !H1_q[7]);


--D1L01 is gepan:u3|i57~618
--operation mode is normal

D1L01 = !D1L21 & (D1L73 # D1L9 & !D1L41);


--E1L44 is number:u4|i~1200
--operation mode is normal

E1L44 = !H3_q[1] # !H3_q[2];


--E1L02 is number:u4|i~0
--operation mode is normal

E1L02 = H3_q[0] # E1L44 # !H3_q[3] # !H3_q[4];


--M3_cs_buffer[3] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M3_cs_buffer[3] = H5_q[5] $ M3_cout[2];

--M3_cout[3] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M3_cout[3] = CARRY(H5_q[5] # M3_cout[2]);


--M3_cs_buffer[2] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M3_cs_buffer[2] = H5_q[4] $ M3_cout[1];

--M3_cout[2] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M3_cout[2] = CARRY(H5_q[4] & M3_cout[1]);


--M3_cs_buffer[1] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M3_cs_buffer[1] = H5_q[3] $ M3_cout[0];

--M3_cout[1] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M3_cout[1] = CARRY(H5_q[3] & M3_cout[0]);


--M3_cs_buffer[0] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

M3_cs_buffer[0] = H5_q[2];

--M3_cout[0] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

M3_cout[0] = CARRY(H5_q[2]);


--F1L841 is move:u5|i~7060
--operation mode is normal

F1L841 = M3_cs_buffer[1] & (!H1_q[4] & !M3_cs_buffer[0] # !H1_q[5]) # !M3_cs_buffer[1] & !H1_q[4] & !M3_cs_buffer[0] & !H1_q[5];


--F1L941 is move:u5|i~7061
--operation mode is normal

F1L941 = F1L891 & (H1_q[6] $ !M3_cs_buffer[2]) # !F1L891 & F1L841 & (H1_q[6] $ !M3_cs_buffer[2]);


--M3_cs_buffer[4] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M3_cs_buffer[4] = H5_q[6] $ M3_cout[3];

--M3_cout[4] is move:u5|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M3_cout[4] = CARRY(H5_q[6] # M3_cout[3]);


--F1L051 is move:u5|i~7062
--operation mode is normal

F1L051 = H1_q[9] & M3L41 & (H1_q[8] $ M3_cs_buffer[4]) # !H1_q[9] & !M3L41 & (H1_q[8] $ M3_cs_buffer[4]);


--F1L091 is move:u5|i~7150
--operation mode is normal

F1L091 = (H1_q[7] $ !M3_cs_buffer[3] # !F1L051 # !F1L941) & CASCADE(F1L791);


--F1L151 is move:u5|i~7064
--operation mode is normal

F1L151 = !H1_q[9] & (H1_q[8] $ !H5_q[6]);


--F1L251 is move:u5|i~7065
--operation mode is normal

F1L251 = H5_q[6] & !H1_q[9] & !H1_q[8];


--F1L351 is move:u5|i~7066
--operation mode is normal

F1L351 = F1L151 & (H1_q[7] $ !H5_q[5]);


--F1L451 is move:u5|i~7067
--operation mode is normal

F1L451 = F1L251 # F1L351 & H5_q[4] & !H1_q[6];


--F1L551 is move:u5|i~7068
--operation mode is normal

F1L551 = !F1L451 & (H1_q[7] # !F1L151 # !H5_q[5]);


--F1L651 is move:u5|i~7070
--operation mode is normal

F1L651 = H5_q[3] & (H5_q[2] & !H1_q[4] # !H1_q[5]) # !H5_q[3] & H5_q[2] & !H1_q[4] & !H1_q[5];


--F1L751 is move:u5|i~7071
--operation mode is normal

F1L751 = F1L991 & (H1_q[6] $ !H5_q[4]) # !F1L991 & F1L651 & (H1_q[6] $ !H5_q[4]);


--F1L191 is move:u5|i~7151
--operation mode is normal

F1L191 = (H1_q[7] $ H5_q[5] # !F1L151 # !F1L751) & CASCADE(F1L551);


--M6_cs_buffer[6] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M6_cs_buffer[6] = H2_q[7] $ M6_cout[5];

--M6_cout[6] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M6_cout[6] = CARRY(H2_q[7] & M6_cout[5]);


--M6_cs_buffer[4] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M6_cs_buffer[4] = H2_q[5] $ M6_cout[3];

--M6_cout[4] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M6_cout[4] = CARRY(H2_q[5] & M6_cout[3]);


--M6_cs_buffer[3] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M6_cs_buffer[3] = H2_q[4] $ M6_cout[2];

--M6_cout[3] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M6_cout[3] = CARRY(H2_q[4] & M6_cout[2]);


--M6_cs_buffer[2] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M6_cs_buffer[2] = H2_q[3] $ M6_cout[1];

--M6_cout[2] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M6_cout[2] = CARRY(H2_q[3] # M6_cout[1]);


--M6_cs_buffer[1] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M6_cs_buffer[1] = H2_q[2] $ M6_cout[0];

--M6_cout[1] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M6_cout[1] = CARRY(H2_q[2] & M6_cout[0]);


--F1L851 is move:u5|i~7075
--operation mode is normal

F1L851 = H1_q[3] & (M6_cs_buffer[2] # H1_q[2] & !M6_cs_buffer[1]) # !H1_q[3] & M6_cs_buffer[2] & H1_q[2] & !M6_cs_buffer[1];


--F1L951 is move:u5|i~7076
--operation mode is normal

F1L951 = F1L102 & (H1_q[4] $ !M6_cs_buffer[3]) # !F1L102 & F1L851 & (H1_q[4] $ !M6_cs_buffer[3]);


--M6_cs_buffer[5] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M6_cs_buffer[5] = H2_q[6] $ M6_cout[4];

--M6_cout[5] is move:u5|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M6_cout[5] = CARRY(H2_q[6] & M6_cout[4]);


--F1L061 is move:u5|i~7077
--operation mode is normal

F1L061 = H1_q[7] & M6_cs_buffer[6] & (H1_q[6] $ !M6_cs_buffer[5]) # !H1_q[7] & !M6_cs_buffer[6] & (H1_q[6] $ !M6_cs_buffer[5]);


--F1L291 is move:u5|i~7152
--operation mode is normal

F1L291 = (H1_q[5] $ M6_cs_buffer[4] # !F1L061 # !F1L951) & CASCADE(F1L002);


--F1L161 is move:u5|i~7079
--operation mode is normal

F1L161 = H2_q[7] & H2_q[6] & H2_q[3] & !F1L431;


--F1L261 is move:u5|i~7080
--operation mode is normal

F1L261 = H2_q[7] & H2_q[6] & (H2_q[4] # H2_q[5]);


--F1L361 is move:u5|i~7081
--operation mode is normal

F1L361 = F1L161 # H2_q[9] # H2_q[8] # F1L261;


--F1L05 is move:u5|i988~43
--operation mode is normal

F1L05 = (!K3_unreg_res_node[6] & (!H