vga_800_600.vhd

VGA彩色信号控制器设计：用VHDL语言编写程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vga_800_600 IS
 PORT(clk : IN STD_LOGIC;
      hs,vs,r,g,b : out std_logic;
      rgb_in : in std_logic_vector(2 downto 0);
      hcnt_out : out std_logic_vector(9 downto 0);
      vcnt_out : out std_logic_vector(9 downto 0));
end entity vga_800_600;
architecture one of vga_800_600 is
signal hcnt : std_logic_vector(9 downto 0);
signal vcnt : std_logic_vector(9 downto 0);
begin
hcnt_out<=hcnt;
vcnt_out<=vcnt;
process(clk)
begin
if clk'event and clk ='1' then
   if hcnt=1040 then
      hcnt<=(others=>'0');
   else hcnt<=hcnt+1;
   end if;
end if;
end process;
process(clk)
begin
if clk'event and clk ='1' then 
   if hcnt=856 then
      if vcnt=666 then
         vcnt<=(others=>'0');
      else vcnt<=vcnt+1;
      end if;
    end if;
end if;
end process;
process(clk)
begin
if clk'event and clk ='1' then
   if ((hcnt>=856)and(hcnt<976)) then
     hs<='0';
   else hs<='1';
   end if;
end if;
end process;
process(clk)
begin
if clk'event and clk ='1' then
  if ((vcnt>=637)and(vcnt<643)) then
    vs<='0';
  else vs<='1';
  end if;
end if;
end process;
process(clk)
begin
if clk'event and clk ='1' then
  if ((hcnt<800) and (vcnt<600)) then
    r<=rgb_in(2);
    g<=rgb_in(1);
    b<=rgb_in(0);
  else r<='0';
       g<='0';
       b<='0';
  end if;
end if;
end process;
end architecture one;