dds1.v

来自「verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii」· Verilog 代码 · 共 32 行

//Call by module DDC 
module dds1(clk, reset, fcontrol, qcosout, qsinout);
  input	        clk;
  input	        reset;
  input  [31:0] fcontrol;
  output [11:0] qcosout;
  output [11:0] qsinout;

  wire   [11:0] xiangwei;
  wire   [11:0] rom_sin_out;
  wire   [11:0] rom_cos_out;

  assign qcosout = rom_cos_out;
  assign qsinout = rom_sin_out;

rom_cos1 rom_cos1(
         .clock(clk),
         .address(xiangwei),
         .q(rom_cos_out));

rom_sin1 rom_sin1(
         .clock(clk),
         .address(xiangwei),
         .q(rom_sin_out));

acc32local acc32local(
         .clk(clk),
         .reset(reset),
         .fcon(fcontrol),
         .xiangwei(xiangwei));

endmodule