acc32local.v

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用

//Call by module dds1
module acc32local(fcon,clk,xiangwei,reset);
  input         clk;
  input  [31:0] fcon;
  input         reset;
  output [11:0] xiangwei;

  reg    [31:0] temp1;

assign xiangwei = temp1[31:20];

always @(posedge clk or posedge reset)
  begin
    if(reset)
      begin 
        temp1 = 0;
      end
    else
      begin
        temp1 = temp1 + fcon;
      end  
  end

endmodule