nco_sinetab.xco

基于XILINX ISE下的数字上变频设计

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = ..\HDL\Modulator\DUC
SET speedgrade = -10
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc4vlx60
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff1148
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex4
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Sine-Cosine_Look-Up_Table family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET output_symmetry=Symmetric
CSET create_rpm=false
CSET output_width=14
CSET memory_type=Block_ROM
CSET theta_input_width=10
CSET clock_enable=false
CSET sclr_pin=false
CSET negative_sine=false
CSET pipeline_stages=1
CSET component_name=nco_sinetab
CSET output_options=Non_Registered
CSET negative_cosine=false
CSET function=Sine_and_Cosine
CSET input_options=Non_Registered
CSET handshaking_enabled=false
CSET aclr_pin=false
# END Parameters
GENERATE