nco_sinetab.v

基于XILINX ISE下的数字上变频设计

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file nco_sinetab.v when simulating
// the core, nco_sinetab. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module nco_sinetab(
	THETA,
	CLK,
	SINE,
	COSINE);


input [9 : 0] THETA;
input CLK;
output [13 : 0] SINE;
output [13 : 0] COSINE;

// synopsys translate_off

      C_SIN_COS_V5_0 #(
		0,	// c_enable_rlocs
		0,	// c_has_aclr
		0,	// c_has_ce
		1,	// c_has_clk
		0,	// c_has_nd
		0,	// c_has_rdy
		0,	// c_has_rfd
		0,	// c_has_sclr
		1,	// c_latency
		1,	// c_mem_type
		0,	// c_negative_cosine
		0,	// c_negative_sine
		2,	// c_outputs_required
		14,	// c_output_width
		1,	// c_pipe_stages
		0,	// c_reg_input
		0,	// c_reg_output
		1,	// c_symmetric
		10)	// c_theta_width
	inst (
		.THETA(THETA),
		.CLK(CLK),
		.SINE(SINE),
		.COSINE(COSINE),
		.ND(),
		.CE(),
		.ACLR(),
		.SCLR(),
		.RFD(),
		.RDY());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of nco_sinetab is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of nco_sinetab is "black_box"

endmodule