m.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
entity M is 
port (m :in std_logic_vector (4 downto 0);
      x : out std_logic_vector(17 downto 0)
       );
end m;
architecture behave of m is 
begin 
    process(m)
      begin
       case m is
        when "00000"=> x<="000000000000000000";
        when "00001"=> x<="000000000000000001";
        when "00010"=> x<="000000000000000010";
        when "00011"=> x<="000000000000000100";
        when "00100"=> x<="000000000000001000";
        when "00101"=> x<="000000000000010000";
        when "00110"=> x<="000000000000100000";
        when "00111"=> x<="000000000001000000";
        when "01000"=> x<="000000000010000000";
        when "01001"=> x<="000000000100000000";
        when "01010"=> x<="000000001000000000";
        when "01011"=> x<="000000010000000000";
        when "01100"=> x<="000000100000000000";
        when "01101"=> x<="000001000000000000";
        when "01110"=> x<="000010000000000000";
        when "01111"=> x<="000100000000000000";
        when "10000"=> x<="001000000000000000";
        when "10001"=> x<="010000000000000000";
        when "10010"=> x<="100000000000000000";
        when  others=> x<="000000000000000000";
      end case;
end process;
  end behave;