shuju.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity shuju is
   port(
        q2:out std_logic_vector(16 downto 0);
        q3:out std_logic_vector(13 downto 0);
        q4:out std_logic_vector(9 downto 0);
        q5:out std_logic_vector(6 downto 0);
        q6:out std_logic_vector(3 downto 0)
        );
   end shuju;
architecture act of shuju is
  begin 
    
     q2<="11000011010100000";
     q3<="10011100010000";
     q4<="1111101000";
     q5<="1100100";
     q6<="1010";
     end act;