hanshu.hier_info

用FPGA做的DDS函数信号发生器

|hanshu
adc <= inst7.DB_MAX_OUTPUT_PORT_TYPE
clk => inst7.IN0
clk => sM:inst5.clock
clk => JIA:inst3.clock
out[0] <= sM:inst5.q[0]
out[1] <= sM:inst5.q[1]
out[2] <= sM:inst5.q[2]
out[3] <= sM:inst5.q[3]
out[4] <= sM:inst5.q[4]
out[5] <= sM:inst5.q[5]
out[6] <= sM:inst5.q[6]
out[7] <= sM:inst5.q[7]
out[8] <= sM:inst5.q[8]
out[9] <= sM:inst5.q[9]
cp => ADDER4B:inst11.cp
r => ADDER4B:inst11.r
m[0] => M:inst.m[0]
m[1] => M:inst.m[1]
m[2] => M:inst.m[2]
m[3] => M:inst.m[3]
m[4] => M:inst.m[4]
p[0] <= shuchu2:inst17.q[0]
p[1] <= shuchu2:inst17.q[1]
p[2] <= shuchu2:inst17.q[2]
p[3] <= shuchu2:inst17.q[3]
p[4] <= shuchu2:inst17.q[4]
p[5] <= shuchu2:inst17.q[5]
p[6] <= shuchu2:inst17.q[6]
p[7] <= shuchu2:inst17.q[7]
p[8] <= shuchu2:inst17.q[8]
p[9] <= shuchu2:inst17.q[9]
p[10] <= shuchu2:inst17.q[10]
p[11] <= shuchu2:inst17.q[11]
p[12] <= shuchu2:inst17.q[12]
p[13] <= shuchu2:inst17.q[13]
p[14] <= shuchu2:inst17.q[14]
p[15] <= shuchu2:inst17.q[15]
p[16] <= shuchu2:inst17.q[16]
p[17] <= shuchu2:inst17.q[17]
p[18] <= shuchu2:inst17.q[18]
p[19] <= shuchu2:inst17.q[19]
xuanzhe => last:inst1.xuanzhe


|hanshu|sM:inst5
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|hanshu|sM:inst5|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_pov:auto_generated.address_a[0]
address_a[1] => altsyncram_pov:auto_generated.address_a[1]
address_a[2] => altsyncram_pov:auto_generated.address_a[2]
address_a[3] => altsyncram_pov:auto_generated.address_a[3]
address_a[4] => altsyncram_pov:auto_generated.address_a[4]
address_a[5] => altsyncram_pov:auto_generated.address_a[5]
address_a[6] => altsyncram_pov:auto_generated.address_a[6]
address_a[7] => altsyncram_pov:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_pov:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_pov:auto_generated.q_a[0]
q_a[1] <= altsyncram_pov:auto_generated.q_a[1]
q_a[2] <= altsyncram_pov:auto_generated.q_a[2]
q_a[3] <= altsyncram_pov:auto_generated.q_a[3]
q_a[4] <= altsyncram_pov:auto_generated.q_a[4]
q_a[5] <= altsyncram_pov:auto_generated.q_a[5]
q_a[6] <= altsyncram_pov:auto_generated.q_a[6]
q_a[7] <= altsyncram_pov:auto_generated.q_a[7]
q_a[8] <= altsyncram_pov:auto_generated.q_a[8]
q_a[9] <= altsyncram_pov:auto_generated.q_a[9]
q_b[0] <= <GND>


|hanshu|sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT


|hanshu|chuan1:inst4
m[0] => ~NO_FANOUT~
m[1] => ~NO_FANOUT~
m[2] => ~NO_FANOUT~
m[3] => ~NO_FANOUT~
m[4] => ~NO_FANOUT~
m[5] => ~NO_FANOUT~
m[6] => ~NO_FANOUT~
m[7] => ~NO_FANOUT~
m[8] => ~NO_FANOUT~
m[9] => ~NO_FANOUT~
m[10] => ~NO_FANOUT~
m[11] => ~NO_FANOUT~
m[12] => ~NO_FANOUT~
m[13] => ~NO_FANOUT~
m[14] => ~NO_FANOUT~
m[15] => ~NO_FANOUT~
m[16] => x[0].DATAIN
m[17] => x[1].DATAIN
m[18] => x[2].DATAIN
m[19] => x[3].DATAIN
m[20] => x[4].DATAIN
m[21] => x[5].DATAIN
m[22] => x[6].DATAIN
m[23] => x[7].DATAIN
x[0] <= m[16].DB_MAX_OUTPUT_PORT_TYPE
x[1] <= m[17].DB_MAX_OUTPUT_PORT_TYPE
x[2] <= m[18].DB_MAX_OUTPUT_PORT_TYPE
x[3] <= m[19].DB_MAX_OUTPUT_PORT_TYPE
x[4] <= m[20].DB_MAX_OUTPUT_PORT_TYPE
x[5] <= m[21].DB_MAX_OUTPUT_PORT_TYPE
x[6] <= m[22].DB_MAX_OUTPUT_PORT_TYPE
x[7] <= m[23].DB_MAX_OUTPUT_PORT_TYPE


|hanshu|JIA:inst3
clock => lpm_add_sub:lpm_add_sub_component.clock
dataa[0] => lpm_add_sub:lpm_add_sub_component.dataa[0]
dataa[1] => lpm_add_sub:lpm_add_sub_component.dataa[1]
dataa[2] => lpm_add_sub:lpm_add_sub_component.dataa[2]
dataa[3] => lpm_add_sub:lpm_add_sub_component.dataa[3]
dataa[4] => lpm_add_sub:lpm_add_sub_component.dataa[4]
dataa[5] => lpm_add_sub:lpm_add_sub_component.dataa[5]
dataa[6] => lpm_add_sub:lpm_add_sub_component.dataa[6]
dataa[7] => lpm_add_sub:lpm_add_sub_component.dataa[7]
dataa[8] => lpm_add_sub:lpm_add_sub_component.dataa[8]
dataa[9] => lpm_add_sub:lpm_add_sub_component.dataa[9]
dataa[10] => lpm_add_sub:lpm_add_sub_component.dataa[10]
dataa[11] => lpm_add_sub:lpm_add_sub_component.dataa[11]
dataa[12] => lpm_add_sub:lpm_add_sub_component.dataa[12]
dataa[13] => lpm_add_sub:lpm_add_sub_component.dataa[13]
dataa[14] => lpm_add_sub:lpm_add_sub_component.dataa[14]
dataa[15] => lpm_add_sub:lpm_add_sub_component.dataa[15]
dataa[16] => lpm_add_sub:lpm_add_sub_component.dataa[16]
dataa[17] => lpm_add_sub:lpm_add_sub_component.dataa[17]
dataa[18] => lpm_add_sub:lpm_add_sub_component.dataa[18]
dataa[19] => lpm_add_sub:lpm_add_sub_component.dataa[19]
dataa[20] => lpm_add_sub:lpm_add_sub_component.dataa[20]
dataa[21] => lpm_add_sub:lpm_add_sub_component.dataa[21]
dataa[22] => lpm_add_sub:lpm_add_sub_component.dataa[22]
dataa[23] => lpm_add_sub:lpm_add_sub_component.dataa[23]
datab[0] => lpm_add_sub:lpm_add_sub_component.datab[0]
datab[1] => lpm_add_sub:lpm_add_sub_component.datab[1]
datab[2] => lpm_add_sub:lpm_add_sub_component.datab[2]
datab[3] => lpm_add_sub:lpm_add_sub_component.datab[3]
datab[4] => lpm_add_sub:lpm_add_sub_component.datab[4]
datab[5] => lpm_add_sub:lpm_add_sub_component.datab[5]
datab[6] => lpm_add_sub:lpm_add_sub_component.datab[6]
datab[7] => lpm_add_sub:lpm_add_sub_component.datab[7]
datab[8] => lpm_add_sub:lpm_add_sub_component.datab[8]
datab[9] => lpm_add_sub:lpm_add_sub_component.datab[9]
datab[10] => lpm_add_sub:lpm_add_sub_component.datab[10]
datab[11] => lpm_add_sub:lpm_add_sub_component.datab[11]
datab[12] => lpm_add_sub:lpm_add_sub_component.datab[12]
datab[13] => lpm_add_sub:lpm_add_sub_component.datab[13]
datab[14] => lpm_add_sub:lpm_add_sub_component.datab[14]
datab[15] => lpm_add_sub:lpm_add_sub_component.datab[15]
datab[16] => lpm_add_sub:lpm_add_sub_component.datab[16]
datab[17] => lpm_add_sub:lpm_add_sub_component.datab[17]
datab[18] => lpm_add_sub:lpm_add_sub_component.datab[18]
datab[19] => lpm_add_sub:lpm_add_sub_component.datab[19]
datab[20] => lpm_add_sub:lpm_add_sub_component.datab[20]
datab[21] => lpm_add_sub:lpm_add_sub_component.datab[21]
datab[22] => lpm_add_sub:lpm_add_sub_component.datab[22]
datab[23] => lpm_add_sub:lpm_add_sub_component.datab[23]
result[0] <= lpm_add_sub:lpm_add_sub_component.result[0]
result[1] <= lpm_add_sub:lpm_add_sub_component.result[1]
result[2] <= lpm_add_sub:lpm_add_sub_component.result[2]
result[3] <= lpm_add_sub:lpm_add_sub_component.result[3]
result[4] <= lpm_add_sub:lpm_add_sub_component.result[4]
result[5] <= lpm_add_sub:lpm_add_sub_component.result[5]
result[6] <= lpm_add_sub:lpm_add_sub_component.result[6]
result[7] <= lpm_add_sub:lpm_add_sub_component.result[7]
result[8] <= lpm_add_sub:lpm_add_sub_component.result[8]
result[9] <= lpm_add_sub:lpm_add_sub_component.result[9]
result[10] <= lpm_add_sub:lpm_add_sub_component.result[10]
result[11] <= lpm_add_sub:lpm_add_sub_component.result[11]
result[12] <= lpm_add_sub:lpm_add_sub_component.result[12]
result[13] <= lpm_add_sub:lpm_add_sub_component.result[13]
result[14] <= lpm_add_sub:lpm_add_sub_component.result[14]
result[15] <= lpm_add_sub:lpm_add_sub_component.result[15]
result[16] <= lpm_add_sub:lpm_add_sub_component.result[16]
result[17] <= lpm_add_sub:lpm_add_sub_component.result[17]
result[18] <= lpm_add_sub:lpm_add_sub_component.result[18]
result[19] <= lpm_add_sub:lpm_add_sub_component.result[19]
result[20] <= lpm_add_sub:lpm_add_sub_component.result[20]