alt_u_div_v2e.tdf

用FPGA做的DDS函数信号发生器

	add_sub_4 : add_sub_am8;
	add_sub_5 : add_sub_bm8;
	add_sub_6 : add_sub_cm8;
	add_sub_7 : add_sub_dm8;
	add_sub_8 : add_sub_em8;
	add_sub_9 : add_sub_mn8;
	DenominatorIn[377..0]	: WIRE;
	DenominatorIn_tmp[377..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[419..0]	: WIRE;
	NumeratorIn[419..0]	: WIRE;
	NumeratorIn_tmp[419..0]	: WIRE;
	prestg[359..0]	: WIRE;
	quotient_tmp[19..0]	: WIRE;
	sel[356..0]	: WIRE;
	selnose[419..0]	: WIRE;
	StageIn[377..0]	: WIRE;
	StageIn_tmp[377..0]	: WIRE;
	StageOut[359..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[19..19];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[18..18], NumeratorIn[38..38]);
	add_sub_1.datab[1..0] = DenominatorIn[19..18];
	add_sub_10.dataa[] = ( StageIn[189..180], NumeratorIn[209..209]);
	add_sub_10.datab[10..0] = DenominatorIn[190..180];
	add_sub_11.dataa[] = ( StageIn[208..198], NumeratorIn[228..228]);
	add_sub_11.datab[11..0] = DenominatorIn[209..198];
	add_sub_12.dataa[] = ( StageIn[227..216], NumeratorIn[247..247]);
	add_sub_12.datab[12..0] = DenominatorIn[228..216];
	add_sub_13.dataa[] = ( StageIn[246..234], NumeratorIn[266..266]);
	add_sub_13.datab[13..0] = DenominatorIn[247..234];
	add_sub_14.dataa[] = ( StageIn[265..252], NumeratorIn[285..285]);
	add_sub_14.datab[14..0] = DenominatorIn[266..252];
	add_sub_15.dataa[] = ( StageIn[284..270], NumeratorIn[304..304]);
	add_sub_15.datab[15..0] = DenominatorIn[285..270];
	add_sub_16.dataa[] = ( StageIn[303..288], NumeratorIn[323..323]);
	add_sub_16.datab[16..0] = DenominatorIn[304..288];
	add_sub_17.dataa[] = ( StageIn[322..306], NumeratorIn[342..342]);