sign_div_unsign_lhg.tdf

用FPGA做的DDS函数信号发生器

--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=7 denominator numerator quotient remainder
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_abs 2005:08:16:22:24:32:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_divide 2005:03:24:00:40:32:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


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FUNCTION alt_u_div_1td (denominator[3..0], numerator[6..0])
RETURNS ( den_out[3..0], quotient[6..0], remainder[3..0]);
FUNCTION add_sub_8i8 (cin, dataa[3..0], datab[3..0])
RETURNS ( result[3..0]);

--synthesis_resources = lut 5 
SUBDESIGN sign_div_unsign_lhg
( 
	denominator[3..0]	:	input;
	numerator[6..0]	:	input;
	quotient[6..0]	:	output;
	remainder[3..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_1td;
	adder : add_sub_8i8;
	gnd_wire	: WIRE;
	norm_num[6..0]	: WIRE;
	protect_quotient[6..0]	: WIRE;
	protect_remainder[3..0]	: WIRE;

BEGIN 
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	adder.cin = gnd_wire;
	adder.dataa[] = denominator[];
	adder.datab[] = protect_remainder[];
	gnd_wire = B"0";
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
END;
--VALID FILE