tr5.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 10 行

library ieee;
use ieee.std_logic_1164.all;
entity tr5 is
   port(p:in std_logic_vector(13 downto 0);
        q:out std_logic_vector(3 downto 0));
   end tr5;
architecture act of tr5 is
  begin 
     q<=p(3 downto 0);
end act;