chuan1.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 10 行

library ieee;
use ieee.std_logic_1164.all;
entity chuan1 is
   port(m:in std_logic_vector(23 downto 0);
        x:out std_logic_vector(7 downto 0));
   end chuan1;
architecture act of chuan1 is
  begin 
     x<=m(23 downto 16);
end act;