tr4.vhd

用FPGA做的DDS函数信号发生器

library ieee;
use ieee.std_logic_1164.all;
entity tr4 is
   port(p:in std_logic_vector(16 downto 0);
        q:out std_logic_vector(3 downto 0));
   end tr4;
architecture act of tr4 is
  begin 
     q<=p(3 downto 0);
end act;