shuchu2.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
entity shuchu2 is
   port(p1:in std_logic_vector(3 downto 0);
        p2:in std_logic_vector(3 downto 0);
        p3:in std_logic_vector(3 downto 0);
        p4:in std_logic_vector(3 downto 0);
        p5:in std_logic_vector(3 downto 0);
        p6:in std_logic_vector(3 downto 0);
        q:out std_logic_vector(19 downto 0));
   end shuchu2;
architecture act of shuchu2 is
  signal shu:std_logic_vector(19 downto 0);
  begin 
     process(p1,p2,p3,p4,p5,p6)
        begin
           if p6="0000" then
              shu<=p5&p4&p3&p2&p1;
           else shu<=p6&p5&p4&p3&p2;end if;
          q<=shu;
        end process;
     end act;