last1.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity last1 is 
    port (
      m2 :in unsigned (23 downto 0);
      m3 :out std_logic);
    end last1;
ARCHITECTURE ART OF last1 IS
begin
  process (m2)
   begin 
    if (m2>=8388608 ) then 
      m3<='1';
    else m3<='0';
    end if ;
end process;
end art;