romsin.v

来自「基于NCO的数字控制振荡器。带测试程序」· Verilog 代码 · 共 25 行

module RomSin (clk, en, addr, data);
	localparam					DSIZE = 12;
	localparam					ASIZE = 12;
	localparam					DEPTH = 2 ** ASIZE;

	input						clk;
	input						en;
	input		[ASIZE-1:0]		addr;
	output		[DSIZE-1:0]		data;
	
	(* ram_init_file = {"rom_sin_12_12", ".mif"} *)
	reg			[DSIZE-1:0]		rom [0:DEPTH-1];
	reg			[DSIZE-1:0]		data;
	
	initial begin
		$readmemh ({"rom_sin_12_12", ".txt"}, rom, 0, DEPTH-1);
		data <= 0;
	end

	always @ (posedge clk) begin
		if (en)
			data <= rom [addr];
	end
endmodule