romnco.v

来自「基于NCO的数字控制振荡器。带测试程序」· Verilog 代码 · 共 27 行

module RomNCO (clk, reset, en, phi, f, out_i, out_q);
	input					clk;
	input					reset;
	input					en;
	input signed	[15:0]	phi;
	input signed	[31:0]	f;
	output signed	[11:0]	out_i, out_q;

	wire signed 	[11:0]	phi_0;
	reg signed		[31:0]	phase;
	
	RomCos RomCos (clk, en, phi_0, out_i);
	RomSin RomSin (clk, en, phi_0, out_q);

	assign phi_0 = phase [31:20] + phi [15:4];
	
	always @ (posedge clk or posedge reset) begin
		if (reset) begin
			phase <= 0;
		end
		else if (en) begin
				phase <= phase + f;
			end
	end
endmodule