codicnco.v

来自「基于CORDIC算法的」· Verilog 代码 · 共 32 行

module CodicNCO (clk, reset, en, phi, f, out_i, out_q);
	input						clk;
	input						reset;
	input						en;
	input signed	[15:0]		phi;
	
	input signed	[31:0]		f;
	output signed	[15:0]		out_i;
	output signed	[15:0]		out_q;

	wire signed 	[15:0]		phi_0;
	reg signed		[31:0]		phase;
	
	sc_corproc sc_corproc(
			.clk(clk),
			.ena(en),
			.Ain(phi_0),
			.sin(out_i),
			.cos(out_q));

	assign phi_0 = phase [31:16] + phi [15:0];
	
	always @ (posedge clk or posedge reset) begin
		if (reset) begin
			phase <= 0;
		end
		else if (en) begin
			phase <= phase + f;
		end
	end
endmodule