tb_sc_corproc.vhd

来自「基于CORDIC算法的」· VHDL 代码 · 共 64 行

-- Testbench for CodicNCO
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_sc_corproc is

end entity tb_sc_corproc;

architecture rtl of tb_sc_corproc is

component sc_corproc is
  port(
    clk : in std_logic;
    ena : in std_logic;
    Ain : in signed(15 downto 0);

    sin : out signed(15 downto 0);
    cos : out signed(15 downto 0));
end component sc_corproc;

signal clk : std_logic;                                      
signal ena : std_logic;                    
signal Ain : signed(15 downto 0);
signal sin : signed(15 downto 0); 
signal cos : signed(15 downto 0);

begin
  dut : sc_corproc
  port map(
    clk => clk,
    ena => ena,                     
    Ain => Ain,                    
    sin => sin,
    cos => open);

process
  begin
    clk <= '0';
  wait for 10 ns;
    clk <= '1';
  wait for 10 ns;
end process;

process
  begin
    ena <= '0';
  wait for 50 ns;
    ena <= '1';
  wait;
end process;

process(clk)
begin
  if(ena='1')then
    Ain <= X"0000";
  elsif(clk'event and clk='1')then
    Ain <= Ain+1;
  end if;
end process;

end architecture rtl;