tb_codicnco.vhd

来自「基于CORDIC算法的」· VHDL 代码 · 共 66 行

-- Testbench for CodicNCO
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_CodicNCO is

end entity tb_CodicNCO;

architecture rtl of tb_CodicNCO is

component CodicNCO is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    en    : in std_logic;
    phi   : in signed(15 downto 0);
    f     : in signed(31 downto 0);
    out_i : out signed(15 downto 0);
    out_q : out signed(15 downto 0));
end component CodicNCO;

signal clk   : std_logic;                    
signal reset : std_logic;                    
signal en    : std_logic;                    
signal phi   : signed(15 downto 0);
signal f     : signed(31 downto 0);
signal out_i : signed(15 downto 0); 
signal out_q : signed(15 downto 0);

begin
  dut : CodicNCO
  port map(
    clk   => clk,
    reset => reset, 
    en    => en,                     
    phi   => phi,                    
    f     => f,
    out_i => out_i,
    out_q => out_q);

process
  begin
    clk <= '0';
  wait for 10 ns;
    clk <= '1';
  wait for 10 ns;
end process;

process
  begin
    reset <= '1';
    en <= '0';
  wait for 30 ns;
    reset <= '0';
  wait for 20 ns;
    en <= '1';
  wait;
end process;

  phi <= X"1CCC";
  f   <= X"11012D00";


end architecture rtl;