📄 register.h
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/******************************************************************
* Copyright (C), 2005-2007, HISILICON Tech. Co., Ltd. *
* *
* File name: *
* OnChipRom.h *
* *
* Description: OnChipRom head file ,include register define *
* *
* Author: *
* ChenYingguo(61362) *
* Version: *
* v1.0 *
* *
* Function List: *
* *
* Date: *
* *
* History: *
* *
*******************************************************************/
#ifndef INCHI6810_H
#define INCHI6810_H
/* #define RUN_IN_FLASH */
//#define HISI3610_CHIP
/* #define CACHE_ENABLE
#define ARM_PLL_CNTRL */
#ifdef HISI3610_CHIP
#define USE_UART4
#else
#define USE_UART0
#endif
/* end of build define */
#ifdef HISI3610_CHIP
#define ECS_ITCM_BASE_ADDR 0x04000000
#define ECS_ITCM_SIZE 0x00002000
#define ECS_DTCM_BASE_ADDR 0x04002000
#define ECS_DTCM_SIZE 0x00002000
/************ 0x10140000-0x1014FFFF *** VIC *******************/
#define ECS_VIC_BASE 0x20030000
#define ECS_VIC_SIZE 0x00010000
/************* 0x10150000-0x101DFFFF *** undefined *************/
/************** APB base address ***********************/
#define ECS_APB_BASE 0x20040000
#define ECS_APB_SIZE 0x00040000
/************* APB BRG1 BASE addresses ***********************/
#define ECS_APBBRG1_BASE 0x30080000
#define ECS_APBBRG1_SIZE 0x00040000
/************* APB BRG2 BASE addresses ***********************/
#define ECS_APBBRG2_BASE 0x300C0000
#define ECS_APBBRG2_SIZE 0x00040000
/************* 0x00000000-0x000FFFFF ** Nand Flash *************/
#define NANDC_DATA_BASE_ADDR 0x30100000
/************* 0xA0010000-0xFFFFFFFF *** undefined *************/
#define SYS_CONTROL_LCD_BASE_ADDRESS 0x20040058
/* Define CLCDC, SSP, SYSCONTROL Device Registers and Framebuffer Base Address */
#define EDC_LCD_SLAVE 0x30200000
#define SYS_CLCDC_BASE_ADDRESS 0x20002000
#define SYS_LCD_CLCDC_BASE_ADDRESS 0x30400000
#define SYS_LCD_FRAMEBUFFER_BASE_ADDRESS 0x30500000
#define SYS_EDC_BASE_ADDRESS 0x20001000
#else
#define ECS_ITCM_BASE_ADDR 0x00000000
#define ECS_ITCM_SIZE 0x00004000
#define ECS_DTCM_BASE_ADDR 0x00004000
#define ECS_DTCM_SIZE 0x00002000
/************ 0x10140000-0x1014FFFF *** VIC *******************/
#define ECS_VIC_BASE 0x10140000
#define ECS_VIC_SIZE 0x00010000
/************* 0x10150000-0x101DFFFF *** undefined *************/
/************** APB base address ***********************/
#define ECS_APB_BASE 0x91040000
#define ECS_APB_SIZE 0x00040000
/************* APB BRG1 BASE addresses ***********************/
#define ECS_APBBRG1_BASE 0x920c0000
#define ECS_APBBRG1_SIZE 0x00040000
/************* APB BRG2 BASE addresses ***********************/
#define ECS_APBBRG2_BASE 0x920c0000
#define ECS_APBBRG2_SIZE 0x00040000
/************* 0x92100000-0x921FFFFF ** Nand Flash *************/
#define NANDC_DATA_BASE_ADDR 0x92100000
/************* 0xA0010000-0xFFFFFFFF *** undefined *************/
#define SYS_CONTROL_LCD_BASE_ADDRESS 0x91040058
/* Define CLCDC, SSP, SYSCONTROL Device Registers and Framebuffer Base Address */
#define EDC_LCD_SLAVE 0x92200000
#define SYS_CLCDC_BASE_ADDRESS 0x91002000
#define SYS_LCD_CLCDC_BASE_ADDRESS 0x92400000
#define SYS_LCD_FRAMEBUFFER_BASE_ADDRESS 0x92500000
#define SYS_EDC_BASE_ADDRESS 0x91001000
/************* MDDR Control register **************************/
#define MDDRC_BASE_ADDR 0x91010000
/*SPC chip define*/
/************** 0x101E0000-0x101EFFFF *** system controller ????具体寄存器位待更新???*****************/
#define SPC_SYSTEM_CONTROL_BASE 0x101E0000
#define SPC_SYSTEM_CONTROL_SIZE 0x00001000
/* SysCtrl register definitions */
#define SYSCTRL_SCCTRL (SPC_SYSTEM_CONTROL_BASE + 0x00000000)
#define SYSCTRL_SCSYSSTAT (SPC_SYSTEM_CONTROL_BASE + 0x00000004)
#define SYSCTRL_SCITMCTRL (SPC_SYSTEM_CONTROL_BASE + 0x00000008)
#define SYSCTRL_SCIMSTAT (SPC_SYSTEM_CONTROL_BASE + 0x0000000C)
#define SYSCTRL_SCXTALCTRL (SPC_SYSTEM_CONTROL_BASE + 0x00000010)
#define SYSCTRL_SCPLLCTRL (SPC_SYSTEM_CONTROL_BASE + 0x00000014)
#define SYSCTRL_SCPLLFCTRL (SPC_SYSTEM_CONTROL_BASE + 0x00000018)
#define SYSCTRL_SCPERCTRL0 (SPC_SYSTEM_CONTROL_BASE + 0x0000001C)
#define SYSCTRL_SCPERCTRL1 (SPC_SYSTEM_CONTROL_BASE + 0x00000020)
#define SYSCTRL_SCPEREN (SPC_SYSTEM_CONTROL_BASE + 0x00000024)
#define SYSCTRL_SCPERDIS (SPC_SYSTEM_CONTROL_BASE + 0x00000028)
#define SYSCTRL_SCPERCLKEN (SPC_SYSTEM_CONTROL_BASE + 0x0000002C)
#define SYSCTRL_SCPERSTAT (SPC_SYSTEM_CONTROL_BASE + 0x00000030)
#define SYSCTRL_SCPERCTRL2 (SPC_SYSTEM_CONTROL_BASE + 0x00000034)
#define SYSCTRL_SCPERCTRL3 (SPC_SYSTEM_CONTROL_BASE + 0x00000038)
#define SYSCTRL_SCPERCTRL4 (SPC_SYSTEM_CONTROL_BASE + 0x0000003C)
#define SYSCTRL_SCPERCTRL5 (SPC_SYSTEM_CONTROL_BASE + 0x00000040)
/************** APB base address ***********************/
#define SPC_ECS_APB_BASE 0x101E0000
#define SPC_ECS_APB_SIZE 0x00009000
/************ 0x101E2000-0x101E3FFF *** TIMER *****************/
#define SPC_TIMER1_BASE (SPC_ECS_APB_BASE + 0x00002000)
#define SPC_TIMER2_BASE (SPC_ECS_APB_BASE + 0x00002020)
#define SPC_TIMER3_BASE (SPC_ECS_APB_BASE + 0x00003000)
#define SPC_TIMER4_BASE (SPC_ECS_APB_BASE + 0x00003020)
#define SPC_TIMER12_SIZE 0x00001000
#define SPC_TIMER34_SIZE 0x00001000
/************* 0x101E4000-0x101E7FFF *** GPIO 0,1,2,3 **********/
#define SPC_GPIO0_BASE (SPC_ECS_APB_BASE + 0x4000)
#define SPC_GPIO1_BASE (SPC_ECS_APB_BASE + 0x5000)
#define SPC_GPIO2_BASE (SPC_ECS_APB_BASE + 0x6000)
#define SPC_GPIO3_BASE (SPC_ECS_APB_BASE + 0x7000)
#define SPC_GPIO4_BASE (SPC_ECS_APB_BASE + 0x10000 + 0x7000)
#define SPC_GPIO5_BASE (SPC_ECS_APB_BASE + 0x10000 + 0x8000)
#define SPC_GPIO6_BASE (SPC_ECS_APB_BASE + 0x10000 + 0x9000)
#define SPC_GPIO7_BASE (SPC_ECS_APB_BASE + 0x10000 + 0xa000)
/************* APB DMA BASE addresses ***********************/
#define SPC_ECS_APBDMA_BASE 0x101F0000
#define SPC_ECS_APBDMA_SIZE 0x100F0000
/************* 0x101F1000-0x101F3FFF *** UART 0-2 **************/
#define SPC_UART0_BASE (ECS_APBDMA_BASE + 0x00001000)
#define SPC_UART1_BASE (ECS_APBDMA_BASE + 0x00002000)
#define SPC_UART2_BASE (ECS_APBDMA_BASE + 0x00003000)
#define SPC_UARTx_SIZE 0x00001000
#endif
/************ 0x101E2000-0x101E3FFF *** TIMER *****************/
#define TIMER1_BASE (ECS_APB_BASE + 0x00003000)
#define TIMER2_BASE (ECS_APB_BASE + 0x00003020)
#define TIMER3_BASE (ECS_APB_BASE + 0x00005000)
#define TIMER4_BASE (ECS_APB_BASE + 0x00005020)
#define TIMER12_SIZE 0x00001000
#define TIMER34_SIZE 0x00001000
/************* 0x101E4000-0x101E7FFF *** GPIO 0,1,2,3 **********/
#define GPIO_ADDR_GROUP0 (ECS_APB_BASE + 0x6000)
#define GPIO_ADDR_GROUP1 (ECS_APB_BASE + 0x7000)
#define GPIO_ADDR_GROUP2 (ECS_APB_BASE + 0x8000)
#define GPIO_ADDR_GROUP3 (ECS_APB_BASE + 0x9000)
#define GPIO_ADDR_GROUP4 (ECS_APB_BASE + 0xA000)
#define GPIO_ADDR_GROUP5 (ECS_APB_BASE + 0xB000)
#define GPIO_ADDR_GROUP6 (ECS_APB_BASE + 0xC000)
#define GPIO_ADDR_GROUP7 (ECS_APB_BASE + 0xD000)
#define GPIO_ADDR_GROUP8 (ECS_APB_BASE + 0xE000)
#define GPIO_ADDR_GROUP9 (ECS_APB_BASE + 0xF000)
#define GPIO_ADDR_GROUP10 (ECS_APB_BASE + 0x10000)
#define GPIO_ADDR_GROUP11 (ECS_APB_BASE + 0x11000)
#define GPIO_ADDR_GROUP12 (ECS_APB_BASE + 0x12000)
#define GPIO_ADDR_GROUP13 (ECS_APB_BASE + 0x13000)
#define SPI1_BASE (ECS_APBBRG1_BASE + 0)
#define SPI2_BASE (ECS_APBBRG2_BASE + 0x5000)
#define SPI3_BASE (ECS_APBBRG2_BASE + 0x6000)
/************* 0x101F1000-0x101F3FFF *** UART 0-2 **************/
#define UART0_BASE 0x101F1000
#define UART1_BASE (ECS_APBBRG1_BASE + 0x1000)
#define UART2_BASE (ECS_APBBRG2_BASE + 0)
#define UART3_BASE (ECS_APBBRG2_BASE + 0x1000)
#define UART4_BASE (ECS_APBBRG2_BASE + 0x2000)
#define UARTx_SIZE 0x00001000
#define SYSTEM_CONTROL_BASE (ECS_APB_BASE + 0)
#define SYSTEM_CONTROL_SIZE 0x00001000
#define HISI3610_SYSCTRL_SCSYSCTRL (SYSTEM_CONTROL_BASE + 0x00000000)
#define HISI3610_SYSCTRL_SCSYSSTAT (SYSTEM_CONTROL_BASE + 0x00000004)
#define HISI3610_SYSCTRL_SCITMCTRL (SYSTEM_CONTROL_BASE + 0x00000008)
#define HISI3610_SYSCTRL_SCIMSTAT (SYSTEM_CONTROL_BASE + 0x0000000C)
#define HISI3610_SYSCTRL_SCXTALCTRL (SYSTEM_CONTROL_BASE + 0x00000010)
#define HISI3610_SYSCTRL_SCPLLCTRL (SYSTEM_CONTROL_BASE + 0x00000014)
#define HISI3610_SYSCTRL_SCPERPLLCTRL (SYSTEM_CONTROL_BASE + 0x00000018)
#define HISI3610_SYSCTRL_SCPERCTRL0 (SYSTEM_CONTROL_BASE + 0x0000001C)
#define HISI3610_SYSCTRL_SCPERCTRL1 (SYSTEM_CONTROL_BASE + 0x00000020)
#define HISI3610_SYSCTRL_SCPEREN (SYSTEM_CONTROL_BASE + 0x00000024)
#define HISI3610_SYSCTRL_SCPERDIS (SYSTEM_CONTROL_BASE + 0x00000028)
#define HISI3610_SYSCTRL_SCPERCLKEN (SYSTEM_CONTROL_BASE + 0x0000002C)
#define HISI3610_SYSCTRL_SCPERSTAT (SYSTEM_CONTROL_BASE + 0x00000030)
#define HISI3610_SYSCTRL_SCPEREN1 (SYSTEM_CONTROL_BASE + 0x00000034)
#define HISI3610_SYSCTRL_SCPERDIS1 (SYSTEM_CONTROL_BASE + 0x00000038)
#define HISI3610_SYSCTRL_SCPERCLKEN1 (SYSTEM_CONTROL_BASE + 0x0000003C)
#define HISI3610_SYSCTRL_SCPERSTAT1 (SYSTEM_CONTROL_BASE + 0x00000040)
#define HISI3610_SYSCTRL_SCRSTCTRL1 (SYSTEM_CONTROL_BASE + 0x00000044)
#define HISI3610_SYSCTRL_SCRSTCTRL2 (SYSTEM_CONTROL_BASE + 0x00000048)
#define HISI3610_SYSCTRL_SCPERCTRL2 (SYSTEM_CONTROL_BASE + 0x0000004C)
#define HISI3610_SYSCTRL_SCPERCTRL3 (SYSTEM_CONTROL_BASE + 0x00000050)
#define HISI3610_SYSCTRL_SCPERCTRL4 (SYSTEM_CONTROL_BASE + 0x00000054)
#define HISI3610_SYSCTRL_SCPERCTRL5 (SYSTEM_CONTROL_BASE + 0x00000058)
#define HISI3610_SYSCTRL_SCPERCTRL6 (SYSTEM_CONTROL_BASE + 0x0000005C)
#define HISI3610_SYSCTRL_SCSYSSTAT2 (SYSTEM_CONTROL_BASE + 0x00000060)
#define HISI3610_SYSCTRL_SCINTMASK (SYSTEM_CONTROL_BASE + 0x00000064)
#define HISI3610_SYSCTRL_SCINTSTATRAW (SYSTEM_CONTROL_BASE + 0x00000068)
#define HISI3610_SYSCTRL_SCINTSTAT (SYSTEM_CONTROL_BASE + 0x0000006C)
#define HISI3610_SYSCTRL_SCINTCLEAR (SYSTEM_CONTROL_BASE + 0x00000070)
#define HISI3610_SYSCTRL_SCPLLFREQ (SYSTEM_CONTROL_BASE + 0x00000074)
#define HISI3610_SYSCTRL_SCCLKLEV (SYSTEM_CONTROL_BASE + 0x00000078)
#define HISI3610_SYSCTRL_SCPERITIME (SYSTEM_CONTROL_BASE + 0x0000007C)
#define HISI3610_SYSCTRL_SCVOLLEV (SYSTEM_CONTROL_BASE + 0x00000080)
#define HISI3610_SYSCTRL_SCVOLTIME (SYSTEM_CONTROL_BASE + 0x00000084)
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