register.h
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#define HISI3610_SYSCTRL_SCVOLTIME32K (SYSTEM_CONTROL_BASE + 0x00000088)
#define HISI3610_SYSCTRL_SCDDRTIME (SYSTEM_CONTROL_BASE + 0x0000008C)
#define HISI3610_SYSCTRL_SCSWADDR (SYSTEM_CONTROL_BASE + 0x00000090)
#define HISI3610_SYSCTRL_SCDDRADDR (SYSTEM_CONTROL_BASE + 0x00000094)
#define HISI3610_SYSCTRL_SCDDRDATA (SYSTEM_CONTROL_BASE + 0x00000098)
#define HISI3610_SYSCTRL_SCVOLDOWN32K (SYSTEM_CONTROL_BASE + 0x0000009C)
#define HISI3610_SYSCTRL_SYSINTMASK (SYSTEM_CONTROL_BASE + 0x000000A0)
#define HISI3610_SYSCTRL_SCRAWINTSTAT (SYSTEM_CONTROL_BASE + 0x000000A4)
#define HISI3610_SYSCTRL_SCMASKINTSTAT (SYSTEM_CONTROL_BASE + 0x000000A8)
/******** SSMC *** 0x10100000-0x1010FFFF *******************/
#define ECS_SSMC_CONFIG_REG_BASE 0x10100000
#define ECS_SSMC_CONFIG_REG_SIZE 0x00010000
/* register addresses of all modules are defined in this section */
/* SSMC register description :*/
#define SMBIDCYR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20)
#define SMBWSTRDR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x04)
#define SMBWSTWRR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x08)
#define SMBWSTOENR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x0C)
#define SMBWSTWENR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x10)
#define SMBCR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x14)
#define SMBSR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x18)
#define SMBWSTBRDR(x) (ECS_SSMC_CONFIG_REG_BASE + (x) * 0x20 + 0x1C)
#define SSMCSR (ECS_SSMC_CONFIG_REG_BASE + 0x200)
#define SSMCCR (ECS_SSMC_CONFIG_REG_BASE + 0x204)
/*** MPMC *** 0x10110000-0x1011FFFF ***????? 请赵丹确认 ????? *********************/
#define ECS_MPMC_CONFIG_REG_BASE 0x10110000
#define ECS_MPMC_CONFIG_REG_SIZE 0x00010000
/* MPMC banks memory map */
#define ECS_MPMC_BANK_4_BASE 0x60000000
#define ECS_MPMC_BANK_4_SIZE 0x08000000
#define ECS_MPMC_BANK_0_BASE 0x30000000
#define ECS_MPMC_BANK_0_SIZE 0x04000000
#define ECS_MPMC_BANK_1_BASE 0x34000000
#define ECS_MPMC_BANK_1_SIZE 0x04000000
#define ECS_MPMC_BANK_2_BASE 0x38000000
#define ECS_MPMC_BANK_2_SIZE 0x04000000
#define ECS_MPMC_BANK_3_BASE 0x3c000000
#define ECS_MPMC_BANK_3_SIZE 0x04000000
/* MPMC register description: */
#define MPMC_CONTROL (ECS_MPMC_CONFIG_REG_BASE)
#define MPMC_STATUS (ECS_MPMC_CONFIG_REG_BASE + 0x004)
#define MPMC_CONFIG (ECS_MPMC_CONFIG_REG_BASE + 0x008)
#define MPMC_DYNAMIC_CONTROL (ECS_MPMC_CONFIG_REG_BASE + 0x020)
#define MPMC_DYNAMIC_REFRESH (ECS_MPMC_CONFIG_REG_BASE + 0x024)
#define MPMC_DYNAMIC_READCONFIG (ECS_MPMC_CONFIG_REG_BASE + 0x028)
#define MPMC_DYNAMIC_TRP (ECS_MPMC_CONFIG_REG_BASE + 0x030)
#define MPMC_DYNAMIC_TRAS (ECS_MPMC_CONFIG_REG_BASE + 0x034)
#define MPMC_DYNAMIC_TSREX (ECS_MPMC_CONFIG_REG_BASE + 0x038)
#define MPMC_DYNAMIC_TWR (ECS_MPMC_CONFIG_REG_BASE + 0x044)
#define MPMC_DYNAMIC_TRC (ECS_MPMC_CONFIG_REG_BASE + 0x048)
#define MPMC_DYNAMIC_TRFC (ECS_MPMC_CONFIG_REG_BASE + 0x04C)
#define MPMC_DYNAMIC_TXSR (ECS_MPMC_CONFIG_REG_BASE + 0x050)
#define MPMC_DYNAMIC_TRRD (ECS_MPMC_CONFIG_REG_BASE + 0x054)
#define MPMC_DYNAMIC_TMRD (ECS_MPMC_CONFIG_REG_BASE + 0x058)
#define MPMC_DYNAMIC_TCDLR (ECS_MPMC_CONFIG_REG_BASE + 0x05C)
#define MPMC_STATIC_EXTENDEDWAIT (ECS_MPMC_CONFIG_REG_BASE + 0x080)
/* Here x=0..3 .*/
#define MPMC_DYNAMIC_CONFIG(x) (ECS_MPMC_CONFIG_REG_BASE + 0x100 + (x) * 0x20)
#define MPMC_DYNAMIC_RASCAS(x) (ECS_MPMC_CONFIG_REG_BASE + 0x100 + (x) * 0x20 + 0x4)
/* Here x=0..3 .*/
#define MPMC_STATIC_CONFIG(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20)
#define MPMC_STATIC_WAITWEN(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0x4)
#define MPMC_STATIC_WAITOEN(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0x8)
#define MPMC_STATIC_WAITRD(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0xC)
#define MPMC_STATIC_WAITPAGE(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0x10)
#define MPMC_STATIC_WAITWR(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0x14)
#define MPMC_STATIC_WAITTURN(x) (ECS_MPMC_CONFIG_REG_BASE + 0x200 + (x) * 0x20 + 0x18)
/* Here x=0..4 .*/
#define MPMC_AHB_CONTROL(x) (ECS_MPMC_CONFIG_REG_BASE + 0x400 + (x) * 0x20)
#define MPMC_AHB_STATUS(x) (ECS_MPMC_CONFIG_REG_BASE + 0x400 + (x) * 0x20 + 0x04)
#define MPMC_AHB_TIMEOUT(x) (ECS_MPMC_CONFIG_REG_BASE + 0x400 + (x) * 0x20 + 0x08)
/* Nand Flash */
#define NF_DATANUM 0x00
#define NF_WAITC 0x04
#define NF_DEVICE 0x08
#define NF_CFG 0x0C
#define NF_CMD 0x10
#define NF_ADDRL 0x14
#define NF_ADDRH 0x18
#define NF_BUFCFG 0x1C
#define NF_BUFREADY 0x20
#define NF_INTEN 0x24
#define NF_INTSTATUS 0x28
#define NF_INTCLR 0x2C
/* VIC register */
#define VIC_IRQ_STATUS (ECS_VIC_BASE + 0x000)
#define VIC_FIQ_STATUS (ECS_VIC_BASE + 0x004)
#define VIC_RAW_INT (ECS_VIC_BASE + 0x008)
#define VIC_INT_SELECT (ECS_VIC_BASE + 0x00C)
#define VIC_INT_ENABLE (ECS_VIC_BASE + 0x010)
#define VIC_INT_ENABLE_CLR (ECS_VIC_BASE + 0x014)
#define VIC_SOFT_INT (ECS_VIC_BASE + 0x018)
#define VIC_SOFT_INT_CLR (ECS_VIC_BASE + 0x01C)
#define VIC_PROTECTION_ENABLE (ECS_VIC_BASE + 0x020)
#define VIC_VECT_ADDR (ECS_VIC_BASE + 0x030)
#define VIC_DEF_VECT_ADDR (ECS_VIC_BASE + 0x034)
#define VIC_INT_ENABLE_MASK 0xFFFFFFFF
#define VIC_VECT_ADDRX(addr) (ECS_VIC_BASE + 0x100 + addr * 4)
#define VIC_VECT_CNTLX(addr) (ECS_VIC_BASE + 0x200 + addr * 4)
/* MMU Control Register bit allocations */
#define CP_MMU 15
/* #define _ARM_FUNCTION(a) \
.code 32 ;\
.balign 4 ;\
_##a:
*/
#define MMUCR_M_ENABLE (1<<0) /* MMU enable */
#define MMUCR_A_ENABLE (1<<1) /* Address alignment fault enable */
#define MMUCR_C_ENABLE (1<<2) /* (data) cache enable */
#define MMUCR_W_ENABLE (1<<3) /* write buffer enable */
#define MMUCR_PROG32 (1<<4) /* PROG32 */
#define MMUCR_DATA32 (1<<5) /* DATA32 */
#define MMUCR_L_ENABLE (1<<6) /* Late abort on earlier CPUs */
#define MMUCR_BIGEND (1<<7) /* Big-endian (=1), little-endian (=0) */
#define MMUCR_SYSTEM (1<<8) /* System bit, modifies MMU protections */
#define MMUCR_ROM (1<<9) /* ROM bit, modifies MMU protections */
#define MMUCR_F (1<<10) /* Should Be Zero */
#define MMUCR_Z_ENABLE (1<<11) /* Branch prediction enable on 810 */
#define MMUCR_I_ENABLE (1<<12) /* Instruction cache enable */
#define MMUCR_V_ENABLE (1<<13) /* Exception vectors remap to 0xFFFF0000 */
#define MMUCR_ALTVECT MMUCR_V_ENABLE /* alternate vector select */
#define MMUCR_RR_ENABLE (1<<14) /* Round robin cache replacement enable */
#define MMUCR_ROUND_ROBIN MMUCR_RR_ENABLE /* round-robin placement */
#define MMUCR_DISABLE_TBIT (1<<15) /* disable TBIT */
#define MMUCR_ENABLE_DTCM (1<<16) /* Enable Data TCM */
#define MMUCR_ENABLE_ITCM (1<<18) /* Enable Instruction TCM */
#define MMUCR_UNALIGNED_ENABLE (1<<22) /* Enable unaligned access */
#define MMUCR_EXTENDED_PAGE (1<<23) /* Use extended PTE format */
#define MMUCR_VECTORED_INTERRUPT (1<<24) /* Enable VIC Interface */
/* bits in the PSR */
#define V_BIT (1<<28)
#define C_BIT (1<<29)
#define Z_BIT (1<<30)
#define N_BIT (1<<31)
#define I_BIT (1<<7)
#define F_BIT (1<<6)
#define T_BIT (1<<5)
/* mode bits */
#define MODE_SYSTEM32 0x1F
#define MODE_UNDEF32 0x1B
#define MODE_ABORT32 0x17
#define MODE_SVC32 0x13
#define MODE_IRQ32 0x12
#define MODE_FIQ32 0x11
#define MODE_USER32 0x10
/* masks for getting bits from PSR */
#define MASK_MODE 0x0000003F
#define MASK_32MODE 0x0000001F
#define MASK_SUBMODE 0x0000000F
#define MASK_INT 0x000000C0
#define MASK_CC 0xF0000000
#ifdef RUN_IN_FLASH
#define ROM_BASE_ADRS 0x34000000 /* base of Flash/EPROM */
#define ROM_TEXT_ADRS (ROM_BASE_ADRS) /* Code start addr in ROM */
#define FLASH_BASE 0x34000000
#else
#define ROM_BASE_ADRS 0xFFFF0000 /* base of OnChipRom */
#define ROM_TEXT_ADRS (ROM_BASE_ADRS) /* Code start addr in ROM */
#define FLASH_BASE 0xFFFF0000
#endif
#if defined(CPU_940T) || defined(CPU_940T_T) || defined (CPU_926ES)
/*
* All ARM 940T BSPs must define a variable sysCacheUncachedAdrs: a
* pointer to a word that is uncached and is safe to read (i.e. has no
* side effects). This is used by the cacheLib code to perform a read
* (only) to drain the write-buffer. Clearly this address must be present
* within one of the regions created within sysPhysMemDesc, where it must
* be marked as non-cacheable. There are many such addresses we could use
* on the board, but we choose to use an address here that will be
* mapped in on just about all configurations: a safe address within the
* interrupt controller: the IRQ Enabled status register. This saves us
* from having to define a region just for this pointer. This constant
* defined here is used to initialise sysCacheUncachedAdrs in sysLib.c
* and is also used by the startup code in sysALib.s and romInit.s in
* draining the write-buffer.
*/
#define SYS_CACHE_UNCACHED_ADRS VIC_INT_ENABLE /* Praful ARM926 MMU needs for sync. */
#endif /* defined(CPU_940T/940T_T/CPU_926ES) */
/* definitions for the AMBA_UART UART */
#if defined USE_UART0
#define SERIAL_BASE_ADR UART0_BASE /* UART 0 base address */
#elif defined USE_UART1
#define SERIAL_BASE_ADR UART1_BASE /* UART 1 base address */
#elif defined USE_UART2
#define SERIAL_BASE_ADR UART2_BASE /* UART 2 base address */
#elif defined USE_UART3
#define SERIAL_BASE_ADR UART3_BASE /* UART 3 base address */
#elif defined USE_UART4
#define SERIAL_BASE_ADR UART4_BASE /* UART 4 base address */
#else
###error
#endif
/*define the frequence of system accouding to system mode*/
#define SYS_TIMER_CLK (13000000) /* XTAL input is 26MHz */
#define AUX_TIMER_CLK (13000000) /* XTAL input is 26MHz */
/*
* Clock rates depend upon CPU power and work load of application.
* The values below are minimum and maximum allowed by the hardware.
* Note that it takes 1 ticks to reload the 16-bit counter and we don't
* accept values that would mean a zero reload value as we don't know what
* that will do.
* So:
* min frequency = roundup(clock_rate/(max_counter_value)+1)
* max frequency = rounddown(clock_rate/(min_counter_value)+1)
* i.e. SYS_CLK_RATE_MAX (SYS_TIMER_CLK/(1+1))
* However, we must set maxima that are sustainable on a running
* system. Experiments suggest that a 16MHz ECS board can sustain a
* maximum clock rate of 16384. The values below have been
* chosen so that there is a reasonable margin and the BSP passes the
* test suite.
*/
#ifdef SYS_CLK_RATE
#undef SYS_CLK_RATE
#define SYS_CLK_RATE 100 /* Redefine the default system clock rate.*/
#endif
#define SYS_CLK_RATE_MIN (1)
/*if cpu clock is 192KHz,then the minimum rate is 3 */
#define SYS_CLK_RATE_MAX 16384
#define AUX_CLK_RATE_MIN (1)
#define AUX_CLK_RATE_MAX 16384
#define TIMER_RELOAD_TICKS 1
/***c56450 A32D08311 2007-1-8 begin*****/
/*修改原因：增加启动类型存储位置的宏定义*/
#define ITCM_TRIGGER_ADDR 0x2899
/***c56450 A32D08311 2007-1-8 end*****/
/*#include "ambaIntrCtl.h"*/
/* Definition of the Flash connection type.*/
#define PARALLEL /* It means two Flash form a 32bits Flash array. */
#endif /*End of INCHI6810_H */
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