fft_fun_tbw.v

调用FPGA的IP核实现FFT运算

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:45:10 06/04/2008
// Design Name:   fft_fun
// Module Name:   E:/FPGA/FPGA_Prog/study_FFTcore/fft_fun_tbw.v
// Project Name:  study_FFTcore
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fft_fun
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fft_fun_tbw_v;

	// Inputs
	reg [7:0] din_re;
	reg [7:0] din_im;
	reg clk;
	reg rst;
	reg data_load_start;

	// Outputs
	wire [7:0] dout_re;
	wire [7:0] dout_im;
	wire [4:0] blk;
	wire data_valid;

	// Instantiate the Unit Under Test (UUT)
	fft_fun uut (
		.din_re(din_re), 
		.din_im(din_im), 
		.clk(clk), 
		.rst(rst), 
		.data_load_start(data_load_start), 
		.dout_re(dout_re), 
		.dout_im(dout_im), 
		.blk(blk), 
		.data_valid(data_valid)
	);

	initial begin
		// Initialize Inputs
		din_re = 0;
		din_im = 0;
		clk = 0;
		rst = 0;
		data_load_start = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule