transcript

调用FPGA的IP核实现FFT运算

# Reading C:/Modeltech_6.1f/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1f May 12 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do {fft64_tbw_v.fdo} 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006
# -- Compiling module fft64
# -- Compiling module glbl
# 
# Top level modules:
# 	fft64
# 	glbl
# Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006
# -- Compiling module fft64_tbw_v
# 
# Top level modules:
# 	fft64_tbw_v
# Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps fft64_tbw_v glbl 
# Loading work.fft64_tbw_v
# Loading work.fft64
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.VCC
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.GND
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.FDE
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.SRL16E
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.SRLC16E
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT3_L
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT3_D
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT4_L
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT2_L
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT2_D
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT4_D
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.MUXF5
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT4
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.RAMB16
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.ARAMB36_INTERNAL
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.INV
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.FDRE
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT3
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT2
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.FD
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.LUT1
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.FDSE
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.XORCY
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.MUXCY
# Loading d:\Xilinx92i\verilog\mti_se\unisims_ver.DSP48
# Loading work.glbl
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
#                    0done=x busy = x
#                    0done=0 busy = 0
#                  462done=0 busy = 1
#                  930done=1 busy = 0
#                  934done=0 busy = 0
# ** Note: $finish    : fft64_tbw.v(135)
#    Time: 1300 ns  Iteration: 0  Instance: /fft64_tbw_v
# 1
# Break at fft64_tbw.v line 135
# Simulation Breakpoint: 1
# Break at fft64_tbw.v line 135
# MACRO ./fft64_tbw_v.fdo PAUSED at line 15