fft_fun.syr

调用FPGA的IP核实现FFT运算

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: fft_fun.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fft_fun.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fft_fun"
Output Format                      : NGC
Target Device                      : xc4vsx35-10-ff668

---- Source Options
Top Module Name                    : fft_fun
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Use DSP Block                      : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Library Search Order               : fft_fun.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fft64.v" in library work
Compiling verilog file "fft_fun.v" in library work
Module <fft64> compiled
Module <fft_fun> compiled
ERROR:HDLCompilers:247 - "fft_fun.v" line 85 Reference to vector wire 'din_re' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fft_fun.v" line 85 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fft_fun.v" line 86 Reference to vector wire 'din_im' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fft_fun.v" line 86 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fft_fun.v" line 94 Reference to vector wire 'dout_re' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fft_fun.v" line 94 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "fft_fun.v" line 95 Reference to vector wire 'dout_im' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "fft_fun.v" line 95 Illegal left hand side of nonblocking assignment
Analysis of file <"fft_fun.prj"> failed.
--> 

Total memory usage is 115752 kilobytes

Number of errors   :    8 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)