xfft_v4_1_timing_calculator_core_fft64.vhd

调用FPGA的IP核实现FFT运算

-- $RCSfile: xfft_v4_1_timing_calculator.ejava,v $ $Revision: 1.1.4.1 $ $Date: 2007/03/16 10:45:49 $
--  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.
--  This text/file contains proprietary, confidential
--  information of Xilinx, Inc., is distributed under license
--  from Xilinx, Inc., and may be used, copied and/or
--  disclosed only pursuant to the terms of a valid license
--  agreement with Xilinx, Inc.  Xilinx hereby grants you
--  a license to use this text/file solely for design, simulation,
--  implementation and creation of design files limited
--  to Xilinx devices or technologies. Use with non-Xilinx
--  devices or technologies is expressly prohibited and
--  immediately terminates your license unless covered by
--  a separate agreement.
--
--  Xilinx is providing this design, code, or information
--  "as is" solely for use in developing programs and
--  solutions for Xilinx devices.  By providing this design,
--  code, or information as one possible implementation of
--  this feature, application or standard, Xilinx is making no
--  representation that this implementation is free from any
--  claims of infringement.  You are responsible for
--  obtaining any rights you may require for your implementation.
--  Xilinx expressly disclaims any warranty whatsoever with
--  respect to the adequacy of the implementation, including
--  but not limited to any warranties or representations that this
--  implementation is free from claims of infringement, implied
--  warranties of merchantability or fitness for a particular
--  purpose.
--
--  Xilinx products are not intended for use in life support
--  appliances, devices, or systems. Use in such applications are
--  expressly prohibited.
--
--  This copyright and support notice must be retained as part
--  of this text at all times. (c) Copyright 1995-2007 Xilinx, Inc.
--  All rights reserved.
------------------------------------------------------------------------------
-- Description:
-- Timing calculator for FFT v4.1
-- Prints transform times for all allowed point sizes for your generated core
-- in clock cycles and microseconds.
-- Transform times are the minimum time between starting one frame and being
-- able to start the next frame.
-- You need to have access to your XilinxCoreLib library for basic functions.
-- Compile and simulate this file to print the table.
------------------------------------------------------------------------------

-- synthesis translate_off
-- $Id: make_timing_model_pkg.pl,v 1.1.2.3 2007/02/01 18:03:50 andreww Exp 0-
--  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.
--  This text/file contains proprietary, confidential
--  information of Xilinx, Inc., is distributed under license
--  from Xilinx, Inc., and may be used, copied and/or
--  disclosed only pursuant to the terms of a valid license
--  agreement with Xilinx, Inc.  Xilinx hereby grants you
--  a license to use this text/file solely for design, simulation,
--  implementation and creation of design files limited
--  to Xilinx devices or technologies. Use with non-Xilinx
--  devices or technologies is expressly prohibited and
--  immediately terminates your license unless covered by
--  a separate agreement.
--
--  Xilinx is providing this design, code, or information
--  "as is" solely for use in developing programs and
--  solutions for Xilinx devices.  By providing this design,
--  code, or information as one possible implementation of
--  this feature, application or standard, Xilinx is making no
--  representation that this implementation is free from any
--  claims of infringement.  You are responsible for
--  obtaining any rights you may require for your implementation.
--  Xilinx expressly disclaims any warranty whatsoever with
--  respect to the adequacy of the implementation, including
--  but not limited to any warranties or representations that this
--  implementation is free from claims of infringement, implied
--  warranties of merchantability or fitness for a particular
--  purpose.
--
--  Xilinx products are not intended for use in life support
--  appliances, devices, or systems. Use in such applications are
--  expressly prohibited.
--
--  This copyright and support notice must be retained as part
--  of this text at all times. (c) Copyright 2007 Xilinx, Inc.
--  All rights reserved.
--------------------------------------------------------------------------------
-- timing_model_pkg.vhd created automatically by make_timing_model_pkg.pl on Thu Feb 22 14:24:12 GMT 2007
-- Regenerate this file if file ../hdl/pkg.vhd changes.
-- Modifying this file by hand is NOT recommended!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.math_real.ALL;
library XilinxCoreLib;
USE XilinxCoreLib.prims_utils_v9_1.ALL;
USE XilinxCoreLib.pkg_baseblox_v9_1.ALL;

LIBRARY XilinxCoreLib;
USE XilinxCoreLib.pkg_mult_gen_v10_0.ALL;


PACKAGE timing_model_pkg IS

  CONSTANT MAX_NFFT_MAX      : INTEGER := 16;
  CONSTANT NFFT_MAX_WIDTH    : INTEGER := 5;  -- Cannot be used at core top level!
  CONSTANT NFFT_MAX_M1_WIDTH : INTEGER := 4;
  CONSTANT MAX_TWIDDLE_WIDTH : INTEGER := 25;
  CONSTANT DIST_RAM  : INTEGER := 0;
  CONSTANT BLOCK_RAM : INTEGER := 1;
  TYPE T_RESOLVABLE_GENERICS IS (RC_CHANNELS,
                                 RC_HAS_BFP,
                                 RC_HAS_OVFLO,
                                 RC_DATA_MEM_TYPE,
                                 RC_TWIDDLE_MEM_TYPE,
                                 RC_BRAM_STAGES,
                                 RC_FAST_CMPY,
                                 RC_OPTIMIZE,
                                 RC_FAST_SINCOS,
                                 RC_HAS_BYPASS,
                                 RC_ENABLE_RLOCS
                                 );
  TYPE T_RESOLVED_GENERICS IS ARRAY (T_RESOLVABLE_GENERICS'low TO T_RESOLVABLE_GENERICS'high) OF INTEGER;
  TYPE T_SO_FSM_STATES IS (ST_IDLE,          -- Idle, waiting for start SIGNAL
                           ST_LOAD_BEGIN,    -- Indicate that loading is about to start
                           ST_LOAD,          -- Load input data (and unload if bit-reversed)
                           ST_RUN_BEGIN,     -- Indicate that processing is about to start
                           ST_RUN,           -- Perform the FFT transform
                           ST_UNLOAD_BEGIN,  -- Indicate that unloading is about to start
                           ST_UNLOAD         -- Unload output data (natural order only)
                           );
  SUBTYPE T_SO_FSM_STATES_BITREVERSED IS T_SO_FSM_STATES RANGE ST_IDLE TO ST_RUN;
  TYPE T_N_COUNT IS (N_COUNT_NONE,                  -- counter not in use
                     N_COUNT_XN_INDEX,              -- counter used for XN_INDEX output
                     N_COUNT_XK_INDEX,              -- counter used for XK_INDEX output
                     N_COUNT_XN_AND_XK_BITREVERSE,  -- both XN_INDEX and bit-reversed XK_INDEX
                     N_COUNT_ADDR_GEN               -- counter used in address generator for FFT transform
                     );
  CONSTANT SO_BFP_RANGER_LATENCY  : INTEGER := 1;
  CONSTANT SO_BFP_MAXHOLD_LATENCY : INTEGER := 2;
  FUNCTION so_butterfly_latency(FAST_BFY, HAS_INPUT_REG       : INTEGER) RETURN INTEGER;
  FUNCTION so_scale_latency(HAS_SCALING                       : INTEGER) RETURN INTEGER;
  FUNCTION so_round_latency(HAS_ROUNDING                      : INTEGER) RETURN INTEGER;
  FUNCTION so_bfp_scale_gen_latency(HAS_SCALING, HAS_ROUNDING : INTEGER) RETURN INTEGER;
  FUNCTION so_pe_latency(C_FAMILY, C_XDEVICEFAMILY            : STRING; C_DATA_MEM_TYPE, C_HAS_ROUNDING, C_HAS_SCALING, C_NFFT_MAX, C_OUTPUT_WIDTH, C_TWIDDLE_MEM_TYPE, EXPAND_TW_WIDTH, C_FAST_BFY, C_FAST_CMPY : INTEGER) RETURN INTEGER;
  FUNCTION so_data_reuse(NFFT : INTEGER) RETURN INTEGER;
  CONSTANT max_num_of_pe : INTEGER := (MAX_NFFT_MAX+1)/2;
  TYPE     r22_const_array IS ARRAY (0 TO max_num_of_pe) OF INTEGER;  -- 1 longer than max PEs for input & output widths
  FUNCTION get_nfft_min(ARCH, HAS_NFFT, NFFT_MAX : INTEGER) RETURN INTEGER;
  FUNCTION eval(condition                                                                 : BOOLEAN) RETURN INTEGER;
  FUNCTION max_i(a, b                                                                     : INTEGER) RETURN INTEGER;
  FUNCTION min_i(a, b                                                                     : INTEGER) RETURN INTEGER;
  FUNCTION when_else(condition                                                            : BOOLEAN; if_true, if_false : INTEGER) RETURN INTEGER;
  FUNCTION cmult_out_width(C_FAMILY                                                       : STRING; DRFLY_WIDTH, IO_WIDTH, TW_WIDTH : INTEGER) RETURN INTEGER;
  FUNCTION mult_latency_bc(C_FAMILY, C_XDEVICEFAMILY                                      : STRING; OPTIMIZE, A_WIDTH, B_WIDTH, P_WIDTH, ROUND, PIPE_IN, PIPE_MID, PIPE_OUT, C_HAS_SCLR : INTEGER) RETURN INTEGER;
  FUNCTION PE_latency_b(C_FAST_BFY, cmult_delay, C_HAS_MULTS, C_HAS_SCALER, C_HAS_ROUNDER : INTEGER) RETURN INTEGER;
  FUNCTION radix4_dragonfly_latency(C_FAST_BFY : INTEGER) RETURN INTEGER;
  FUNCTION r2_pe_latency(C_FAST_BFY, CMULT_DELAY, C_HAS_SCALER, C_HAS_ROUNDER             : INTEGER) RETURN INTEGER;
  FUNCTION calc_dist_mem_addr_latency (c_family  : STRING; data_mem_depth : INTEGER) RETURN INTEGER;
  FUNCTION calc_dist_mem_mux_latency (c_family   : STRING; data_mem_depth : INTEGER) RETURN INTEGER;
  FUNCTION get_min_mem_delay(c_family, c_xdevicefamily            : STRING; data_mem_type, data_mem_depth : INTEGER) RETURN INTEGER;
  FUNCTION get_mem_delay(c_family, c_xdevicefamily                : STRING; data_mem_type, data_mem_depth, sin_cos_delay, tw_addr_gen_delay, rw_addr_gen_delay, mux_delay, switch_delay : INTEGER) RETURN INTEGER;
  FUNCTION r22_mem_type(nfft_max, bram_stage          : INTEGER) RETURN r22_const_array;
  FUNCTION r22_pe_width(scaling, nfft_max, input_bits : INTEGER) RETURN r22_const_array;
  FUNCTION r22_bf1_delay(OPT_DSP48s, pe_id, HAS_NFFT, NFFT_MAX_EVEN : INTEGER) RETURN INTEGER;
  FUNCTION r22_bf2_delay(OPT_DSP48s, pe_id, HAS_NFFT, NFFT_MAX_EVEN : INTEGER) RETURN INTEGER;
  FUNCTION r22_pe_latency(c_family, C_XDEVICEFAMILY   : STRING; C_FAST_BFY, C_FAST_CMPY, c_fast_sincos, has_nfft, nfft_max, tw_bits, has_scaling, has_rounding, has_mux : INTEGER; width_of_pe, memory_type : r22_const_array) RETURN r22_const_array;
  TYPE T_TWGEN_ARCH IS (TW_BRAM_HALF_SINCOS,  -- block memory, store half-wave sine and cosine
                        TW_BRAM_QUARTER_SIN,  -- block memory, store quarter-wave sine
                        TW_DISTMEM,           -- distributed memory, store 1st and 2nd quarter-wave sine
                        TW_DISTMEM_SO         -- distributed memory, store 1st quarter-wave sine, single-output arch
                        );
  FUNCTION get_twiddle_arch(MEM_TYPE, THETA_WIDTH, TWIDDLE_WIDTH : INTEGER; SINGLE_OUTPUT : BOOLEAN := false) RETURN T_TWGEN_ARCH;
  TYPE T_TWGEN_TABLE IS ARRAY (0 TO (2**MAX_NFFT_MAX)-1) OF STD_LOGIC_VECTOR(MAX_TWIDDLE_WIDTH-1 DOWNTO 0);
  FUNCTION get_twiddle_latency(C_FAMILY, C_XDEVICEFAMILY : STRING; MEM_TYPE, THETA_WIDTH, TWIDDLE_WIDTH : INTEGER; SINGLE_OUTPUT : BOOLEAN := false) RETURN INTEGER;
  CONSTANT ARCH_cmpy_18x18    : INTEGER := 0;
  CONSTANT ARCH_cmpy_35x18    : INTEGER := 1;
  CONSTANT ARCH_cmpy_52x18    : INTEGER := 6;
  CONSTANT ARCH_cmpy_35x35    : INTEGER := 2;
  CONSTANT ARCH_cmpy_3        : INTEGER := 3;
  CONSTANT ARCH_complex_mult3 : INTEGER := 4;
  CONSTANT ARCH_complex_mult4 : INTEGER := 5;
  CONSTANT cmpy_mult18x18_DSP48s : INTEGER := 1;
  CONSTANT cmpy_mult35x18_DSP48s : INTEGER := 2;
  CONSTANT cmpy_mult35x35_DSP48s : INTEGER := 4;
  CONSTANT cmpy18x18_DSP48s      : INTEGER := 4;
  CONSTANT cmpy35x18_DSP48s      : INTEGER := 8;
  CONSTANT cmpy52x18_DSP48s      : INTEGER := 12;
  CONSTANT cmpy35x35_DSP48s      : INTEGER := 16;
  FUNCTION mult_gen_mults(A_WIDTH, B_WIDTH       : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_nov4_3_mults(A_WIDTH, B_WIDTH    : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_nov4_4_mults(A_WIDTH, B_WIDTH    : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_mult_add_DSP48s(A_WIDTH, B_WIDTH : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_3_DSP48_DSP48s(A_WIDTH, B_WIDTH  : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_arch(C_FAMILY, C_XDEVICEFAMILY : STRING; OPTIMIZE, LARGE_WIDTH, SMALL_WIDTH : INTEGER; SINGLE_OUTPUT : INTEGER := 0) RETURN INTEGER;
  FUNCTION cascade_mult35x35(MODE, A_WIDTH, B_WIDTH, C_WIDTH, ROUND_BITS : INTEGER) RETURN BOOLEAN;
  FUNCTION cmpy_mult_add_latency(C_XDEVICEFAMILY : STRING; A_WIDTH, B_WIDTH, C_WIDTH, ROUND_BITS, MODE, PIPE_IN, PIPE_MID, PIPE_OUT : INTEGER) RETURN INTEGER;
  FUNCTION mult_latency(C_FAMILY, C_XDEVICEFAMILY                                                         : STRING; A_WIDTH, B_WIDTH : INTEGER) RETURN INTEGER;
  FUNCTION cmpy18x18_latency(PIPE_IN, PIPE_MID, PIPE_OUT                                                  : INTEGER) RETURN INTEGER;
  FUNCTION cmpy35x18_latency(C_XDEVICEFAMILY : STRING; PIPE_IN, PIPE_MID, PIPE_OUT                                                  : INTEGER) RETURN INTEGER;
  FUNCTION cmpy52x18_latency(C_XDEVICEFAMILY : STRING; PIPE_IN, PIPE_MID, PIPE_OUT                                                  : INTEGER) RETURN INTEGER;
  FUNCTION cmpy35x35_latency(C_XDEVICEFAMILY : STRING; PIPE_IN, PIPE_MID, PIPE_OUT                                                  : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_3_DSP48_latency(C_XDEVICEFAMILY : STRING; A_WIDTH, B_WIDTH, P_WIDTH, ROUND, PIPE_IN, PIPE_MID, PIPE_OUT             : INTEGER) RETURN INTEGER;
  FUNCTION cmpy_latency(C_FAMILY, C_XDEVICEFAMILY : STRING; OPTIMIZE, A_WIDTH, B_WIDTH, P_WIDTH, ROUND, PIPE_IN, PIPE_MID, PIPE_OUT, C_HAS_SCLR : INTEGER; SINGLE_OUTPUT : INTEGER := 0) RETURN INTEGER;

END timing_model_pkg;


PACKAGE BODY timing_model_pkg IS

  FUNCTION so_butterfly_latency(FAST_BFY, HAS_INPUT_REG : INTEGER) RETURN INTEGER IS
    VARIABLE result                 : INTEGER;
    -- Need an extra register after the 'fast' butterfly to ease the route from
    -- the DSP48s to slice logic
    CONSTANT FABRIC_OUTPUT_REGISTER : INTEGER := 1;
  BEGIN
    -- FAST_BFY is only ever 1 for families that support DSP48-based butterflies
    -- so there is no need to check family here
    IF FAST_BFY = 1 THEN
      result := 1 + HAS_INPUT_REG + FABRIC_OUTPUT_REGISTER;  -- HAS_INPUT_REG must be 1 or 0 only; PREG = 1; MREG not used
    ELSE
      result := 1;  -- Fabric adders have single cycle latency
    END IF;
    RETURN result;
  END so_butterfly_latency;

  FUNCTION so_scale_latency(HAS_SCALING : INTEGER) RETURN INTEGER IS
  BEGIN
    IF HAS_SCALING = 1 THEN
      RETURN 1;
    ELSE
      RETURN 0;
    END IF;
  END so_scale_latency;