core_fft64.xco

调用FPGA的IP核实现FFT运算

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#
# Xilinx Core Generator version J.36
# Date: Wed Jun 04 01:44:05 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx35
SET devicefamily = virtex4
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff668
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 4.1
# END Select
# BEGIN Parameters
CSET ce=true
CSET channels=1
CSET component_name=core_fft64
CSET fast_butterfly=true
CSET fast_complex_mult=true
CSET implementation_options=radix_4_burst_io
CSET input_width=8
CSET memory_options_data=block_ram
CSET memory_options_phase_factors=block_ram
CSET number_of_stages_using_block_ram_for_data_and_phase_factors=0
CSET optimize_for_speed_using_xtreme_dsp_slices=true
CSET output_ordering=natural_order
CSET ovflo=false
CSET phase_factor_width=8
CSET rounding_modes=convergent_rounding
CSET run_time_configurable_transform_length=false
CSET scaling_options=block_floating_point
CSET sclr=true
CSET target_clock_frequency=250
CSET target_data_throughput=50
CSET transform_length=64
# END Parameters
GENERATE
# CRC: dfe928a4