core_fft64_readme.txt

调用FPGA的IP核实现FFT运算

The following files were generated for 'core_fft64' in directory 
E:\FPGA\FPGA_Prog\study_FFTcore:

core_fft64.asy:
   Graphical symbol information file. Used by the ISE tools and some
   third party tools to create a symbol representing the core.

core_fft64.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

core_fft64.sym:
   Please see the core data sheet.

core_fft64.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

core_fft64.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

core_fft64.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

core_fft64.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

core_fft64.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

core_fft64_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

core_fft64_readme.txt:
   Text file indicating the files generated and how they are used.

core_fft64_xfft_v4_1_xst_1_vhdl.prj:
   Please see the core data sheet.

core_fft64_xmdf.tcl:
   Please see the core data sheet.

xfft_v4_1_timing_calculator_core_fft64.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.