xiic_i.h

FPGA 并行NOR FLash的操作相关

/******************************************************************************
*
* This macro flushes the receive FIFO such that all bytes contained within it
* are discarded.
*
* @param	InstancePtr is a pointer to the IIC instance containing the FIFO
*		to be flushed.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mFlushRxFifo(XIic *InstancePtr);
*
******************************************************************************/
#define XIic_mFlushRxFifo(InstancePtr)                                     \
{                                                                           \
    int LoopCnt;                                                            \
    u8 Temp;                                                            \
    u8 BytesToRead = XIo_In8(InstancePtr->BaseAddress +              \
                                 XIIC_RFO_REG_OFFSET) + 1;                  \
    for(LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++)                      \
    {                                                                       \
        Temp = XIo_In8(InstancePtr->BaseAddress + XIIC_DRR_REG_OFFSET);  \
    }                                                                       \
}

/******************************************************************************
*
* This macro flushes the transmit FIFO such that all bytes contained within it
* are discarded.
*
* @param	InstancePtr is a pointer to the IIC instance containing the FIFO
*		to be flushed.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mFlushTxFifo(XIic *InstancePtr);
*
******************************************************************************/
#define XIic_mFlushTxFifo(InstancePtr);                                    \
{                                                                           \
    u8 CntlReg = XIo_In8(InstancePtr->BaseAddress +                  \
                             XIIC_CR_REG_OFFSET);                           \
    XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET,              \
             CntlReg | XIIC_CR_TX_FIFO_RESET_MASK);                         \
    XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);    \
}

/******************************************************************************
*
* This macro reads the next available received byte from the receive FIFO
* and updates all the data structures to reflect it.
*
* @param	InstancePtr is a pointer to the IIC instance to be operated on.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mReadRecvByte(XIic *InstancePtr);
*
******************************************************************************/
#define XIic_mReadRecvByte(InstancePtr)                                    \
{                                                                           \
    *InstancePtr->RecvBufferPtr++ =                                         \
        XIo_In8(InstancePtr->BaseAddress + XIIC_DRR_REG_OFFSET);         \
    InstancePtr->RecvByteCount--;                                           \
    InstancePtr->Stats.RecvBytes++;                                         \
}

/******************************************************************************
*
* This macro writes the next byte to be sent to the transmit FIFO
* and updates all the data structures to reflect it.
*
* @param	InstancePtr is a pointer to the IIC instance to be operated on.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mWriteSendByte(XIic *InstancePtr);
*
******************************************************************************/
#define XIic_mWriteSendByte(InstancePtr)                                   \
{                                                                           \
    XIo_Out8(InstancePtr->BaseAddress + XIIC_DTR_REG_OFFSET,             \
        *InstancePtr->SendBufferPtr++);                                     \
    InstancePtr->SendByteCount--;                                           \
    InstancePtr->Stats.SendBytes++;                                         \
}

/******************************************************************************
*
* This macro sets up the control register for a master receive operation.
* A write is necessary if a 10 bit operation is being performed.
*
* @param	InstancePtr is a pointer to the IIC instance to be operated on.
* @param	ControlRegister contains the contents of the IIC device control
*		register
* @param	ByteCount contains the number of bytes to be received for the
*		master receive operation
*
* @return	None.
*
* @note		Signature:
*		void XIic_mSetControlRegister(XIic *InstancePtr,
*						u8 ControlRegister,
*						int ByteCount);
*
******************************************************************************/
#define XIic_mSetControlRegister(InstancePtr, ControlRegister, ByteCount)  \
{                                                                           \
    (ControlRegister) &= ~(XIIC_CR_NO_ACK_MASK | XIIC_CR_DIR_IS_TX_MASK);   \
    if (InstancePtr->Options & XII_SEND_10_BIT_OPTION)                      \
    {                                                                       \
        (ControlRegister) |= XIIC_CR_DIR_IS_TX_MASK;                        \
    }                                                                       \
    else                                                                    \
    {                                                                       \
        if ((ByteCount) == 1)                                               \
        {                                                                   \
            (ControlRegister) |= XIIC_CR_NO_ACK_MASK;                       \
        }                                                                   \
    }                                                                       \
}

/******************************************************************************
*
* This macro enters a critical region by disabling the global interrupt bit
* in the Global interrupt register.
*
* @param	BaseAddress is the base address of the IIC device.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mEnterCriticalRegion(u32 BaseAddress)
*
******************************************************************************/
#define XIic_mEnterCriticalRegion(BaseAddress)  \
	XIIC_GINTR_DISABLE(BaseAddress)

/******************************************************************************
*
* This macro exits a critical region by enabling the global interrupt bit
* in the Global interrupt register.
*
* @param	BaseAddress is the base address of the IIC device.
*
* @return	None.
*
* @note		Signature:
*		void XIic_mExitCriticalRegion(u32 BaseAddress)
*
******************************************************************************/
#define XIic_mExitCriticalRegion(BaseAddress)  \
	XIIC_GINTR_ENABLE(BaseAddress)

/******************************************************************************
*
* This macro clears the statistics of an instance such that it can be common
* such that some parts of the driver may be optional.
*
* @param	InstancePtr is a pointer to the IIC instance to be operated on.
*
* @return	None.
*
* @note		Signature:
*		void XIIC_CLEAR_STATS(XIic *InstancePtr)
*
******************************************************************************/
#define XIIC_CLEAR_STATS(InstancePtr)                                   \
{                                                                       \
    u8 NumBytes;                                                    \
    u8 *DestPtr;                                                    \
                                                                        \
    DestPtr = (u8 *)&InstancePtr->Stats;                            \
    for (NumBytes = 0; NumBytes < sizeof(XIicStats); NumBytes++)        \
    {                                                                   \
        *DestPtr++ = 0;                                                 \
    }                                                                   \
}

/************************** Function Prototypes ******************************/

extern XIic_Config XIic_ConfigTable[];

/* The following variables are shared across files of the driver and
 * are function pointers that are necessary to break dependencies allowing
 * optional parts of the driver to be used without condition compilation
 */
extern void (*XIic_AddrAsSlaveFuncPtr) (XIic * InstancePtr);
extern void (*XIic_NotAddrAsSlaveFuncPtr) (XIic * InstancePtr);
extern void (*XIic_RecvSlaveFuncPtr) (XIic * InstancePtr);
extern void (*XIic_SendSlaveFuncPtr) (XIic * InstancePtr);
extern void (*XIic_RecvMasterFuncPtr) (XIic * InstancePtr);
extern void (*XIic_SendMasterFuncPtr) (XIic * InstancePtr);
extern void (*XIic_ArbLostFuncPtr) (XIic * InstancePtr);
extern void (*XIic_BusNotBusyFuncPtr) (XIic * InstancePtr);

void XIic_TransmitFifoFill(XIic * InstancePtr, int Role);

#ifdef __cplusplus
}
#endif

#endif /* end of protection macro */