xiic_dyn_master.c

FPGA 并行NOR FLash的操作相关

/* $Id: xiic_dyn_master.c,v 1.1 2007/12/03 15:44:58 meinelte Exp $ */
/******************************************************************************
*
*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*       FOR A PARTICULAR PURPOSE.
*
*       (c) Copyright 2006 Xilinx Inc.
*       All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiic_dyn_master.c
*
* Contains master functions for the XIic component in Dynamic controller mode.
* This file is necessary to send or receive as a master on the IIC bus.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- --- ------- -----------------------------------------------------------
* 1.03a   mta 04/10/06 Created.
* 1.13a wgr  03/22/07 Converted to new coding style.
* </pre>
*
******************************************************************************/

/***************************** Include Files *********************************/

#include "xiic.h"
#include "xiic_i.h"
#include "xio.h"

/************************** Constant Definitions *****************************/

/**************************** Type Definitions *******************************/

/***************** Macros (Inline Functions) Definitions *********************/

/******************************************************************************
*
* This macro includes dynamic master code such that dynamic master operations,
* sending and receiving data, may be used. This function hooks the dynamic
* master processing to the driver such that events are handled properly and
* allows dynamic master processing to be optional. It must be called before any
* functions which are contained in this file are called, such as after the
* driver is initialized.
*
* @note 	None.
*
******************************************************************************/
#define XIIC_DYN_MASTER_INCLUDE                                             \
{                                                                       \
    XIic_RecvMasterFuncPtr = DynRecvMasterData;                            \
    XIic_SendMasterFuncPtr = DynSendMasterData;                            \
}

/******************************************************************************
*
* This macro sends the address for a 7 bit address during both read and write
* operations. It takes care of the details to format the address correctly.
* This macro is designed to be called internally to the drivers.
*
* @param    BaseAddress contains the base address of the IIC Device.
* @param    SlaveAddress contains the address of the slave to send to.
* @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
#define XIic_mDynSend7BitAddress(BaseAddress, SlaveAddress, Operation)       \
{                                                                            \
    u8 LocalAddr = (u8)(SlaveAddress << 1);                          \
    LocalAddr = (LocalAddr & 0xFE) | (Operation);                            \
    XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET - 1,                         \
              XIIC_TX_DYN_START_MASK | LocalAddr);                           \
}

/******************************************************************************
* This macro sends a stop condition on IIC bus for Dynamic logic.
*
* @param    BaseAddress contains the base address of the IIC Device.
* @param    ByteCount is the number of Rx bytes received before the master.
*			doesn't respond with ACK.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
#define XIic_mDynSendStop(BaseAddress, ByteCount)                           \
{                                                                           \
    XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET-1, XIIC_TX_DYN_STOP_MASK |  \
    		  ByteCount); \
}

/************************** Function Prototypes ******************************/

static void DynRecvMasterData(XIic * InstancePtr);
static void DynSendMasterData(XIic * InstancePtr);
static int IsBusBusy(XIic * InstancePtr);

/************************** Variable Definitions *****************************/

/*****************************************************************************/
/**
* This function sends data as a Dynamic master on the IIC bus. If the bus is
* busy, it will indicate so and then enable an interrupt such that the status
* handler will be called when the bus is no longer busy. The slave address is
* sent by using XIic_mDynSend7BitAddress().
*
* @param    InstancePtr points to the Iic instance to be worked on.
* @param    TxMsgPtr points to the data to be transmitted.
* @param    ByteCount is the number of message bytes to be sent.
*
* @return	XST_SUCCESS if successful else XST_FAILURE.
*
* @note		None.
*
******************************************************************************/
int XIic_DynMasterSend(XIic * InstancePtr, u8 *TxMsgPtr, u8 ByteCount)
{
	u8 CntlReg;

	XIic_mEnterCriticalRegion(InstancePtr->BaseAddress);

	/*
	 * Ensure that the Dynamic master processing has been included such that
	 * events will be properly handled.
	 */
	XIIC_DYN_MASTER_INCLUDE;
	InstancePtr->IsDynamic = TRUE;

	/*
	 * If the busy is busy, then exit the critical region and wait for the
	 * bus not to be busy. The function enables the BusNotBusy interrupt.
	 */
	if (IsBusBusy(InstancePtr)) {
		XIic_mExitCriticalRegion(InstancePtr->BaseAddress);

		return XST_FAILURE;
	}

	/*
	 * If it is already a master on the bus (repeated start), the direction was
	 * set to Tx which is throttling bus. The control register needs to be set
	 * before putting data into the FIFO.
	 */
	CntlReg = XIo_In8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET);
	if (CntlReg & XIIC_CR_MSMS_MASK) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |= XIIC_CR_DIR_IS_TX_MASK;
		XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET,
			 CntlReg);
		InstancePtr->Stats.RepeatedStarts++;
	}

	/*
	 * Save message state.
	 */
	InstancePtr->SendByteCount = ByteCount;
	InstancePtr->SendBufferPtr = TxMsgPtr;

	/*
	 * Send the Seven Bit address. Only 7 bit addressing is supported in
	 * Dynamic mode.
	 */
	XIic_mDynSend7BitAddress(InstancePtr->BaseAddress,
				 InstancePtr->AddrOfSlave,
				 XIIC_WRITE_OPERATION);

	/*
	 * Set the transmit address state to indicate the address has been sent for
	 * communication with event driven processing.
	 */
	InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;

	/*
	 * Fill the TX FIFO.
	 */
	if (InstancePtr->SendByteCount > 1) {
		XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
	}

	/*
	 * After filling fifo, if data yet to send > 1, enable Tx