xiic_l.h

FPGA 并行NOR FLash的操作相关

* toggle on write functionality meaning any bits which are set in the value
* written cause the bits in the register to change to the opposite state.
*
* This function writes only the specified value to the register such that
* some status bits may be set and others cleared.  It is the caller's
* responsibility to get the value of the register prior to setting the value
* to prevent an destructive behavior.
*
* @param	RegBaseAddress is the base address of the IIC device.
* @param	Status contains the value to be written to the Interrupt
*		status register.
*
* @return	None.
*
* @note		C-Style signature:
*		void XIIC_WRITE_IISR(u32 RegBaseAddress, u32 Status);
*
******************************************************************************/
#define XIIC_WRITE_IISR(RegBaseAddress, Status)				\
	XIo_Out32((RegBaseAddress) + XIIC_IISR_OFFSET, (Status))

/******************************************************************************
*
*
* This function gets the contents of the Interrupt Status Register.
* This register indicates the status of interrupt sources for the device.
* The status is independent of whether interrupts are enabled such
* that the status register may also be polled when interrupts are not enabled.
*
* Each bit of the register correlates to a specific interrupt source within the
* device.  All bits of this register are latched.  Writing a 1 to a bit within
* this register causes an interrupt to be generated if enabled in the interrupt
* enable register and the global interrupt enable is set.  Since the status is
* latched, each status bit must be acknowledged in order for the bit in the
* status register to be updated.  Each bit can be acknowledged by writing a
* 0 to the bit in the status register.

* @param	RegBaseAddress is the base address of the IIC device.
*
* @return	A status which contains the value read from the Interrupt
*		Status Register.
*
* @note		C-Style signature:
*		u32 XIIC_READ_IISR(u32 RegBaseAddress);
*
******************************************************************************/
#define XIIC_READ_IISR(RegBaseAddress) 					\
	XIo_In32((RegBaseAddress) + XIIC_IISR_OFFSET)

/******************************************************************************
*
* This function sets the contents of the Interrupt Enable Register . This
* register controls which interrupt sources of the IIC device are allowed to
* generate an interrupt. The global interrupt enable register and the device
* interrupt enable register must also be set appropriately for an interrupt to be
* passed out of the device.
*
* Each bit of the register correlates to a specific interrupt source within the
* device.  Setting a bit in this register enables the interrupt source to generate
* an interrupt.  Clearing a bit in this register disables interrupt generation
* for that interrupt source.
*
* This function writes only the specified value to the register such that
* some interrupt sources may be enabled and others disabled.  It is the
* caller's responsibility to get the value of the interrupt enable register
* prior to setting the value to prevent a destructive behavior.
*
* @param	RegBaseAddress is the base address of the IIC device.
* @param	Enable contains the value to be written to the Interrupt Enable
*		Register.
*
* @return 	None
*
* @note		C-Style signature:
*		void XIIC_WRITE_IIER(u32 RegBaseAddress, u32 Enable);
*
******************************************************************************/
#define XIIC_WRITE_IIER(RegBaseAddress, Enable)				\
	XIo_Out32((RegBaseAddress) + XIIC_IIER_OFFSET, (Enable))

/******************************************************************************
*
*
* This function gets the Interrupt enable register contents.  This register
* controls which interrupt sources of the device are allowed to generate an
* interrupt.  The global interrupt enable register and the device interrupt
* enable register must also be set appropriately for an interrupt to be
* passed out of the IIC device.
*
* Each bit of the register correlates to a specific interrupt source within the
* IIC device. Setting a bit in this register enables the interrupt source to
* generate an interrupt.  Clearing a bit in this register disables interrupt
* generation for that interrupt source.
*
* @param	RegBaseAddress is the base address of the IIC device.
*
* @return	The contents read from the Interrupt Enable Register.
*
* @note		C-Style signature:
*		u32 XIIC_READ_IIER(u32 RegBaseAddress)
*
******************************************************************************/
#define XIIC_READ_IIER(RegBaseAddress)					\
	XIo_In32((RegBaseAddress) + XIIC_IIER_OFFSET)

/************************** Function Prototypes ******************************/


/******************************************************************************
*
* This macro reads a register in the IIC device using an 8 bit read operation.
* This macro does not do any checking to ensure that the register exists if the
* register may be excluded due to parameterization, such as the GPO Register.
*
* @param	BaseAddress of the IIC device.
* @param	RegisterOffset contains the offset of the register from the
*		device base address.
*
* @return	The value read from the register.
*
* @note		C-Style signature:
* 		u8 XIic_mReadReg(u32 BaseAddress, int RegisterOffset);
*
******************************************************************************/
#define XIic_mReadReg(BaseAddress, RegisterOffset) 			\
	XIo_In8((BaseAddress) + (RegisterOffset))

/******************************************************************************
*
* This macro writes a register in the IIC device using an 8 bit write
* operation. This macro does not do any checking to ensure that the register
* exists if the register may be excluded due to parameterization, such as the
* GPO Register.
*
* @param	BaseAddress of the IIC device.
* @param	RegisterOffset contains the offset of the register from the
*		device base address.
* @param	Data contains the data to be written to the register.
*
* @return	None.
*
* @note		C-Style signature:
*		void XIic_mWriteReg(u32 BaseAddress, int RegisterOffset,
					u8 Data);
*
******************************************************************************/
#define XIic_mWriteReg(BaseAddress, RegisterOffset, Data) 		\
	XIo_Out8((BaseAddress) + (RegisterOffset), (Data))

/******************************************************************************
*
* This macro clears the specified interrupt in the Interrupt status
* register.  It is non-destructive in that the register is read and only the
* interrupt specified is cleared.  Clearing an interrupt acknowledges it.
*
* @param	BaseAddress contains the IIC registers base address.
* @param	InterruptMask contains the interrupts to be disabled
*
* @return	None.
*
* @note		C-Style signature:
*		void XIic_mClearIisr(u32 BaseAddress, u32 InterruptMask);
*
******************************************************************************/
#define XIic_mClearIisr(BaseAddress, InterruptMask)			\
	XIIC_WRITE_IISR((BaseAddress),					\
	XIIC_READ_IISR(BaseAddress) & (InterruptMask))

/******************************************************************************
*
* This macro sends the address for a 7 bit address during both read and write
* operations. It takes care of the details to format the address correctly.
* This macro is designed to be called internally to the drivers.
*
* @param	BaseAddress contains the base address of the IIC Device.
* @param	SlaveAddress contains the address of the slave to send to.
* @param	Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
*
* @return	None.
*
* @note		C-Style signature:
* 		void XIic_mSend7BitAddress(u32 BaseAddress, u8 SlaveAddress,
*						u8 Operation);
*
******************************************************************************/
#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation)	\
{									\
	u8 LocalAddr = (u8)(SlaveAddress << 1);				\
	LocalAddr = (LocalAddr & 0xFE) | (Operation);			\
	XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);		\
}

/******************************************************************************
*
* This macro sends the address for a 7 bit address during both read and write
* operations. It takes care of the details to format the address correctly.
* This macro is designed to be called internally to the drivers.
*
* @param	BaseAddress contains the base address of the IIC Device.
* @param	SlaveAddress contains the address of the slave to send to.
* @param	Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION.
*
* @return	None.
*
* @note		C-Style signature:
* 		void XIic_mDynSend7BitAddress(u32 BaseAddress, u8 SlaveAddress,
*						u8 Operation);
*
******************************************************************************/
#define XIic_mDynSend7BitAddress(BaseAddress, SlaveAddress, Operation)	\
{									\
	u8 LocalAddr = (u8)(SlaveAddress << 1);				\
	LocalAddr = (LocalAddr & 0xFE) | (Operation);			\
	XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET - 1,		\
			XIIC_TX_DYN_START_MASK | LocalAddr);		\
}

/******************************************************************************
*
* This macro sends the address, start and stop for a 7 bit address during both
* write operations. It takes care of the details to format the address
* correctly.
* This macro is designed to be called internally to the drivers.
*
* @param	BaseAddress contains the base address of the IIC Device.
* @param	SlaveAddress contains the address of the slave to send to.
* @param	Operation indicates XIIC_WRITE_OPERATION.
*
* @return	None.
*
* @note		C-Style signature:
* 		void XIic_mDynSendStartStopAddress(u32 BaseAddress,
*							u8 SlaveAddress,
*							u8 Operation);
*
******************************************************************************/
#define XIic_mDynSendStartStopAddress(BaseAddress, SlaveAddress, Operation)  \
{									     \
	u8 LocalAddr = (u8)(SlaveAddress << 1);				     \
	LocalAddr = (LocalAddr & 0xFE) | (Operation);			     \
	XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET - 1,		     \
		XIIC_TX_DYN_START_MASK | XIIC_TX_DYN_STOP_MASK | LocalAddr); \
}

/******************************************************************************
*
* This macro sends a stop condition on IIC bus for Dynamic logic.
*
* @param	BaseAddress contains the base address of the IIC Device.
* @param	ByteCount is the number of Rx bytes received before the master.
*		doesn't respond with ACK.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
#define XIic_mDynSendStop(BaseAddress, ByteCount)			       \
{									       \
	XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET-1, XIIC_TX_DYN_STOP_MASK | \
    		  ByteCount); 						       \
}

/************************** Function Prototypes *****************************/

unsigned XIic_Recv(u32 BaseAddress, u8 Address,
		   u8 *BufferPtr, unsigned ByteCount, u8 Option);

unsigned XIic_Send(u32 BaseAddress, u8 Address,
		   u8 *BufferPtr, unsigned ByteCount, u8 Option);

unsigned XIic_DynRecv(u32 BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount);

unsigned XIic_DynSend(u32 BaseAddress, u16 Address, u8 *BufferPtr,
		      u8 ByteCount, u8 Option);

int XIic_DynInit(u32 BaseAddress);


#ifdef __cplusplus
}
#endif

#endif /* end of protection macro */