xiic_master.c

FPGA 并行NOR FLash的操作相关

/* $Id: xiic_master.c,v 1.1 2007/12/03 15:44:58 meinelte Exp $ */
/******************************************************************************
*
*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*       FOR A PARTICULAR PURPOSE.
*
*       (c) Copyright 2002 Xilinx Inc.
*       All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiic_master.c
*
* Contains master functions for the XIic component. This file is necessary to
* send or receive as a master on the IIC bus.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- --- ------- -----------------------------------------------
* 1.01b jhl 3/27/02 Reparitioned the driver
* 1.01c ecm 12/05/02 new rev
* 1.13a wgr  03/22/07 Converted to new coding style.
* </pre>
*
****************************************************************************/

/***************************** Include Files *******************************/

#include "xiic.h"
#include "xiic_i.h"
#include "xio.h"

/************************** Constant Definitions ***************************/


/**************************** Type Definitions *****************************/


/***************** Macros (Inline Functions) Definitions *******************/

/*****************************************************************************
*
* This macro includes master code such that master operations, sending
* and receiving data, may be used.  This function hooks the master processing
* to the driver such that events are handled properly and allows master
* processing to be optional.  It must be called before any functions which
* are contained in this file are called, such as after the driver is
* initialized.
*
* @note
*
* None
*
******************************************************************************/
#define XIIC_MASTER_INCLUDE                                             \
{                                                                       \
    XIic_RecvMasterFuncPtr = RecvMasterData;                            \
    XIic_SendMasterFuncPtr = SendMasterData;                            \
}

/************************** Function Prototypes ****************************/

static void SendSlaveAddr(XIic * InstancePtr);
static void RecvMasterData(XIic * InstancePtr);
static void SendMasterData(XIic * InstancePtr);
static int IsBusBusy(XIic * InstancePtr);

/************************** Variable Definitions **************************/

/****************************************************************************/
/**
* This function sends data as a master on the IIC bus. If the bus is busy, it
* will indicate so and then enable an interrupt such that the status handler
* will be called when the bus is no longer busy.  The slave address which has
* been set with the XIic_SetAddress() function is the address to which the
* specific data is sent.  Sending data on the bus performs a write operation.
*
* @param    InstancePtr points to the Iic instance to be worked on.
* @param    TxMsgPtr points to the data to be transmitted
* @param    ByteCount is the number of message bytes to be sent
*
* @return
*
* - XST_SUCCESS indicates the message transmission has been initiated.
* - XST_IIC_BUS_BUSY indicates the bus was in use and that the BusNotBusy
*   interrupt is enabled which will update the EventStatus when the bus is no
*   longer busy.
*
* @note
*
* None
*
******************************************************************************/
int XIic_MasterSend(XIic * InstancePtr, u8 *TxMsgPtr, int ByteCount)
{
	u8 CntlReg;

	XIic_mEnterCriticalRegion(InstancePtr->BaseAddress);

	/* Ensure that the master processing has been included such that events
	 * will be properly handled
	 */
	XIIC_MASTER_INCLUDE;
	InstancePtr->IsDynamic = FALSE;

	/*
	 * If the busy is busy, then exit the critical region and wait for the
	 * bus to not be busy, the function enables the bus not busy interrupt
	 */
	if (IsBusBusy(InstancePtr)) {
		XIic_mExitCriticalRegion(InstancePtr->BaseAddress);

		return XST_IIC_BUS_BUSY;
	}

	/* If it is already a master on the bus (repeated start), the direction was
	 * set to tx which is throttling bus.  The control register needs to be set
	 * before putting data into the FIFO
	 */
	CntlReg = XIo_In8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET);

	if (CntlReg & XIIC_CR_MSMS_MASK) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |=
			(XIIC_CR_DIR_IS_TX_MASK | XIIC_CR_REPEATED_START_MASK);

		XIo_Out8(InstancePtr->BaseAddress + XIIC_CR_REG_OFFSET,
			 CntlReg);
		InstancePtr->Stats.RepeatedStarts++;
	}

	/* Save message state
	 */
	InstancePtr->SendByteCount = ByteCount;
	InstancePtr->SendBufferPtr = TxMsgPtr;

	/* Put the address into the FIFO to be sent and indicate that the operation
	 * to be performed on the bus is a write operation, a general call address
	 * handled the same as a 7 bit address even if 10 bit address is selected
	 * Set the transmit address state to indicate the address has been sent
	 */
	if ((InstancePtr->Options & XII_SEND_10_BIT_OPTION) &&
	    (InstancePtr->AddrOfSlave != 0)) {
		XIic_mSend10BitAddrByte1(InstancePtr->AddrOfSlave,
					 XIIC_WRITE_OPERATION);
		XIic_mSend10BitAddrByte2(InstancePtr->AddrOfSlave);
	}
	else {
		XIic_mSend7BitAddr(InstancePtr->AddrOfSlave,
				   XIIC_WRITE_OPERATION);
	}
	/* Set the transmit address state to indicate the address has been sent
	 * for communication with event driven processing
	 */
	InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;

	/* Fill remaining available FIFO with message data
	 */
	if (InstancePtr->SendByteCount > 1) {
		XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
	}

	/* After filling fifo, if data yet to send > 1, enable Tx