rs232_wrapper.vhd

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:03 11/17/2008 
-- Design Name: 
-- Module Name:    rs232_wrapper - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.all;

entity RS232 is
port( Reset, Clock16x, Rxd, Send: in std_logic;
DataIn: in std_logic_vector(7 downto 0);
rxddataclk : out std_logic;
DataOut1: out std_logic_vector (7 downto 0);
Txd: out std_logic);
end RS232;

architecture RS232_Arch of RS232 is

  component Rs232Rxd
  port( Reset, Clock16x, Rxd: in std_logic;
  rxddataclk : out std_logic;
  DataOut1: out std_logic_vector (7 downto 0));
  end component;

  component Rs232Txd
  port( Reset, Send, Clock16x: in std_logic;
  DataIn: in std_logic_vector(7 downto 0);
  Txd: out std_logic);
  end component;

begin
  u1: Rs232Rxd port map(
  Reset => Reset,
  Clock16x => Clock16x,
  Rxd => Rxd,
  rxddataclk => rxddataclk,
  DataOut1 => DataOut1);
  
  u2: Rs232Txd port map(
  Reset => Reset,
  Send => Send,
  Clock16x => Clock16x,
  DataIn => DataIn,
  Txd => Txd);
  
end RS232_Arch;