tb_rs232.vhd

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

library ieee;
use ieee.std_logic_1164.all;
entity tb_TopLevelRS232 is
end tb_TopLevelRS232;

architecture behav of tb_TopLevelRS232 is
component TopLevelRS232
port( Reset, Send, Rxd: in std_logic;
		SystemClock: in std_logic;
		DataIn: in std_logic_vector (7 downto 0);
		An: out std_logic_vector (3 downto 0);
		Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp: out std_logic;
		Txd: out std_logic;
		RxdData: out std_logic_vector (7 downto 0));
end component;

signal tb_reset, tb_send, tb_rxd, tb_systemclock : std_logic;
signal tb_DataIn : std_logic_vector(7 downto 0) ;
signal tb_an : std_logic_vector (3 downto 0);
signal tb_ca, tb_cb, tb_cc, tb_cd, tb_ce, tb_cf, tb_cg, tb_dp :std_logic;
signal tb_txd : std_logic;
signal tb_RxdData : std_logic_vector (7 downto 0);
constant period : time := 6.5 us;
begin

-- unit under test
UUT : TopLevelRS232 port map(
					Reset=>tb_reset,
					Send=>tb_send,
					Rxd=>tb_rxd,
					SystemClock=>tb_systemclock,
					DataIn=>tb_dataIn,
					An=>tb_an,
					Ca=>tb_ca,
					Cb=>tb_cb,
					Cc=>tb_cc,
					Cd=>tb_cd,
					Ce=>tb_ce,
					Cf=>tb_cf,
					Cg=>tb_cg,
					Dp=>tb_dp,
					Txd=>tb_txd,
					RxdData=>tb_RxdData);
					
-- produce clock signal
process
begin
	tb_systemclock <= '1';
wait for period/2;
	tb_systemclock <= '0';
wait for period/2;
end process;

-- produce reset signal
process
begin
tb_reset <= '1';
wait for 1.5*period;
tb_reset <= '0';
wait;
end process;

-- produce data received
process
begin
	tb_rxd <= '1';
wait for 5.5*period;
	tb_rxd <= '0'; -- Start bit
wait for 16*period;
	tb_rxd <= '0'; -- Bit 0
wait for 16*period;
	tb_rxd <= '1'; -- Bit 1
wait for 16*period;
	tb_rxd <= '0'; -- Bit 2
wait for 16*period;
	tb_rxd <= '0'; -- Bit 3
wait for 16*period;
	tb_rxd <= '0'; -- Bit 4
wait for 16*period;
	tb_rxd <= '1'; -- Bit 5
wait for 16*period;
	tb_rxd <= '1'; -- Bit 6
wait for 16*period;
	tb_rxd <= '0'; -- Bit 7
wait for 16*period;
	tb_rxd <= '1'; -- Stop bit
wait for 16*period;

	tb_rxd <= '0'; -- Start bit
wait for 16*period;
	tb_rxd <= '0'; -- Bit 0
wait for 16*period;
	tb_rxd <= '1'; -- Bit 1
wait for 16*period;
	tb_rxd <= '0'; -- Bit 2
wait for 16*period;
	tb_rxd <= '0'; -- Bit 3
wait for 16*period;
	tb_rxd <= '0'; -- Bit 4
wait for 16*period;
	tb_rxd <= '1'; -- Bit 5
wait for 16*period;
	tb_rxd <= '1'; -- Bit 6
wait for 16*period;
	tb_rxd <= '1'; -- Bit 7
wait for 16*period;
	tb_rxd <= '1'; -- Stop bit
wait for 16*period;

	tb_rxd <= '0'; -- Start bit
wait for 16*period;
	tb_rxd <= '0'; -- Bit 0
wait for 16*period;
	tb_rxd <= '1'; -- Bit 1
wait for 16*period;
	tb_rxd <= '0'; -- Bit 2
wait for 16*period;
	tb_rxd <= '0'; -- Bit 3
wait for 16*period;
	tb_rxd <= '0'; -- Bit 4
wait for 16*period;
	tb_rxd <= '1'; -- Bit 5
wait for 16*period;
	tb_rxd <= '1'; -- Bit 6
wait for 16*period;
	tb_rxd <= '0'; -- Bit 7
wait for 16*period;
	tb_rxd <= '1'; -- Stop bit
wait for 16*period;
wait;
end process;

-- produce Send signal
process
begin
	tb_send <= '0';
wait for 200*period;
	tb_send <= '1';
	wait for 160*period;
	tb_send <= '0';
	wait for 64*period;
	tb_send <= '1';
	wait for 160 period;
	tb_send <= '0';
wait for period;
wait;
end process;

-- produce data to be transmitted
process
begin
	tb_dataIn <= x"62";
wait for 360*period;
	tb_dataIn <= x"28";
wait;
end process;
end behav;