toplevelrs232.vhd

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:15 11/17/2008 
-- Design Name: 
-- Module Name:    toplevelrs232 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
entity TopLevelRS232 is
port ( Reset, Send, Rxd: in std_logic;
		SystemClock: in std_logic;
		DataIn: in std_logic_vector (7 downto 0);
		An: out std_logic_vector (3 downto 0);
		Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp: out std_logic;
		Txd: out std_logic;
		RxdData: out std_logic_vector (7 downto 0));
end TopLevelRS232;

architecture Arch of TopLevelRS232 is
component RS232
port( Reset, Clock16x, Rxd, Send: in std_logic;
		DataIn: in std_logic_vector(7 downto 0);
		rxddataclk: out std_logic;
		DataOut1: out std_logic_vector (7 downto 0);
		Txd: out std_logic);
end component;

component D4to7
port ( Q: in std_logic_vector (3 downto 0);
		Seg: out std_logic_vector (6 downto 0));
end component;

component Scan4Digit
port ( Digit3, Digit2, Digit1, Digit0: in std_logic_vector(6 downto 0);
		Clock: in std_logic; An : out std_logic_vector(3 downto 0);
		Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp: out std_logic);
end component;

-- signal iReset, iClock, iClock16x, iReceived: std_logic;
signal iClock16x: std_logic;
signal iDigitOut3, iDigitOut2, iDigitOut1, iDigitOut0: std_logic_vector (6 downto 0);
signal iDataOut1, iDataOut2: std_logic_vector (7 downto 0);
signal iCount9: std_logic_vector (8 downto 0);
signal irxddataclk : std_logic;
begin
-- Added for simulation only to view Rxd data
RxdData <= iDataOut1;
--iDataOut2 <= DataIn;
-- Generate the main clock signals, the frequency of which should be
-- as close to 16 * baudrate as possible
-- For example, for the baudrate of 9600, the frquency of the main
-- clock should be as close to 153600Hz as possible.
-- 50MHz is the only available clock source in Spartan-3 board,
-- the closest RS232 main clock that can be obtained is
-- 153846Hz, which is equal to 50MHz/325.
process (SystemClock)
begin
if SystemClock'event and SystemClock = '1' then
	if Reset = '1' then
		iCount9 <= (others=>'0');
	elsif
		iCount9 = "101000101" then -- the divider is 325, or "101000101"
			iCount9 <= (others=>'0');
		else iCount9 <= iCount9 + '1';
	end if;
end if;
end process;

--iClock16x <= iCount9(8);
-- Simulation only
iClock16x <= SystemClock;

process(irxddataclk)
begin
	if irxddataclk'event and irxddataclk = '1' then
		idataout2 <= idataout1;
	end if;
end process;
		

-- RS232 core
U1: RS232 port map (
	Reset => Reset,
	Clock16x => iClock16x,
	Rxd => Rxd,
	Send => Send,
	DataIn => DataIn,
	DataOut1 => iDataOut1,
	rxddataclk => irxddataclk,
	Txd => Txd);

U2: D4to7 port map (
	Q => iDataOut1(3 downto 0),
	Seg => iDigitOut0);

U3: D4to7 port map (
	Q => iDataOut1(7 downto 4),
	Seg => iDigitOut1);

U4: D4to7 port map (
	Q => iDataOut2(3 downto 0),
	Seg => iDigitOut2);

U5: D4to7 port map (
	Q => iDataOut2(7 downto 4),
	Seg => iDigitOut3);

U6: Scan4Digit port map (
	Digit3 => iDigitOut3,
	Digit2 => iDigitOut2,
	Digit1 => iDigitOut1,
	Digit0 => iDigitOut0,
	Clock => SystemClock,
	An => An,	
	Ca => Ca,
	Cb => Cb,
	Cc => Cc,
	Cd => Cd,
	Ce => Ce,
	Cf => Cf,
	Cg => Cg,
	Dp => Dp);

end Arch;