rs232_txd.vhd

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:24:49 11/17/2008 
-- Design Name: 
-- Module Name:    rs232_txd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Rs232Txd is
	port( Reset, Send, Clock16x: in std_logic;
	DataIn: in std_logic_vector(7 downto 0);
	Txd: out std_logic);
end Rs232Txd;

architecture Rs232Txd_Arch of Rs232Txd is
	attribute enum_encoding: string;
	-- state definitions
	type stateType is (stIdle, stData, stStop, stTxdCompleted);
	attribute enum_encoding of stateType: type is "00 01 11 10";
	signal presState: stateType;
	signal nextState: stateType;
	signal iSend1, iSend2, iReset, iClock1xEnable, iEnableTxdBuffer, iEnableShift: std_logic;
	signal iTxdBuffer: std_logic_vector (8 downto 0) := (others=>'1');
	signal iClockDiv: std_logic_vector (3 downto 0);
	signal iClock1x: std_logic;
	signal iNoBitsSent: std_logic_vector (3 downto 0);

begin

process (Clock16x)
begin

	if Clock16x'event and Clock16x = '1' then
		if Reset = '1' or iReset = '1' then
			iClock1xEnable <= '0';
			iClockDiv <= (others=>'0');
		else
			iSend1 <= Send;
			iSend2 <= iSend1;
		end if;

		if iSend1 = '1' and iSend2 = '0' then
			iClock1xEnable <= '1';
		end if;

		if iClock1xEnable = '1' then
			iClockDiv <= iClockDiv + '1';
		end if;
		
	end if;
end process;

iClock1x <= iClockDiv(3);

process (iClock1xEnable, iClock1x)
begin

	if iClock1xEnable = '0' then
		iNoBitsSent <= (others=>'0');
		presState <= stIdle;
	elsif iClock1x'event and iClock1x = '1' then
		iNoBitsSent <= iNoBitsSent + '1';
		presState <= nextState;
	end if;		
	
	if iClock1x'event and iClock1x = '1' then
		if iEnableTxdBuffer = '1' then
			iTxdBuffer <= DataIn & '0'; -- inserting start bit 
		end if;	
		if iEnableShift = '1' then
			iTxdBuffer <= '1' & iTxdBuffer(8 downto 1);
		end if;
	end if;
end process;
Txd <= iTxdBuffer(0);


process (presState, iClock1xEnable, iNoBitsSent)
begin
-- signal defaults
iReset <= '0';
iEnableTxdBuffer <= '0';
iEnableShift <= '0';
	case presState is
		when stIdle =>
			if iClock1xEnable = '1' then
				iEnableTxdBuffer <= '1';
				nextState <= stData;
			else
				nextState <= stIdle;
			end if;
		when stData =>
			if iNoBitsSent = "1010" then
				nextState <= stStop;
			else
				iEnableShift <= '1';
				nextState <= stData;
			end if;
		when stStop =>
				nextState <= stTxdCompleted;
		when stTxdCompleted =>
				iReset <= '1';
				nextState <= stIdle;
	end case;
end process;


end Rs232Txd_Arch;