count_decount.vhd

c est un compteur et decompteur en vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity Count_Decount is
generic(n:integer:=13);
port (
          clk   : in std_logic;
	     reset  : in std_logic;
	     CD     : out std_logic_vector(n-1 downto 0)
      );

end Count_Decount;

architecture Behavioral of Count_Decount is

constant min : std_logic_vector(n-1 downto 0):="1000000000000";
constant max : std_logic_vector(n-1 downto 0):="0111111111111";
signal CD_int : std_logic_vector(n-1 downto 0);
signal up : std_logic;

begin
process(clk,reset)
begin
if reset='1' 
   then CD_int<= (others=>'0');
   elsif (clk'event and clk='1') 
	   then  
  	      if (CD_int=max-1 )
	         then up<='1';
            elsif  (CD_int=min+1)
		         then up<='0';
      	      else up<=up;
	      end if;
	      if up='0'
	         then CD_int<=CD_int+1;
	         else CD_int<=CD_int-1;
	      end if;
      else CD_int<=CD_int;
end if;
CD<= CD_int;
end process;
end Behavioral;