count60.rpt

一个关于VHDL的cpld开发实验程序

         #  ma2 &  ma3
         # !ma0 &  ma1
         # !ma0 & !ma2
         # !ma0 &  ma3;

-- Node name is ':1445' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ071);
  _EQ071 = !ma0
         # !ma2
         # !ma1 & !ma3
         #  ma1 &  ma3;

-- Node name is '~1449~1' 
-- Equation name is '~1449~1', location is LC3_B14, type is buried.
-- synthesized logic cell 
_LC3_B14 = LCELL( _EQ072);
  _EQ072 =  ma0 & !ma1 &  ma2 & !ma3
         # !ma0 &  ma1 &  ma2 & !ma3;

-- Node name is ':1460' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = LCELL( _EQ073);
  _EQ073 = !_LC1_B14 &  _LC2_B15 & !_LC7_B13
         # !_LC1_B14 & !_LC7_B13 &  _LC7_B14;

-- Node name is ':1493' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = LCELL( _EQ074);
  _EQ074 = !ma2 &  ma3
         #  ma0 &  ma3
         #  ma1 &  ma3;

-- Node name is '~1503~1' 
-- Equation name is '~1503~1', location is LC7_B13, type is buried.
-- synthesized logic cell 
_LC7_B13 = LCELL( _EQ075);
  _EQ075 =  ma1 & !ma2 & !ma3;

-- Node name is ':1508' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ076);
  _EQ076 = !_LC1_B14 &  _LC7_B13
         # !_LC1_B14 &  _LC7_B14
         # !_LC1_B14 &  _LC3_B13;

-- Node name is ':1614' 
-- Equation name is '_LC6_L20', type is buried 
!_LC6_L20 = _LC6_L20~NOT;
_LC6_L20~NOT = LCELL( _EQ077);
  _EQ077 = !mb1
         # !mb0
         # !mb2
         #  mb3;

-- Node name is '~1641~1' 
-- Equation name is '~1641~1', location is LC4_L20, type is buried.
-- synthesized logic cell 
_LC4_L20 = LCELL( _EQ078);
  _EQ078 =  mb0 & !mb1 &  mb2 & !mb3
         # !mb0 &  mb1 &  mb2 & !mb3;

-- Node name is ':1650' 
-- Equation name is '_LC4_L21', type is buried 
_LC4_L21 = LCELL( _EQ079);
  _EQ079 = !mb0 & !mb1 &  mb2 & !mb3;

-- Node name is ':1686' 
-- Equation name is '_LC7_L21', type is buried 
!_LC7_L21 = _LC7_L21~NOT;
_LC7_L21~NOT = LCELL( _EQ080);
  _EQ080 =  mb1
         # !mb0
         #  mb2
         #  mb3;

-- Node name is ':1691' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = LCELL( _EQ081);
  _EQ081 =  mb1 &  mb2
         # !mb0 &  mb1
         #  mb1 & !mb3
         # !mb0 & !mb2
         # !mb0 &  mb3
         #  mb0 &  mb2 & !mb3
         # !mb1 & !mb2 &  mb3;

-- Node name is ':1712' 
-- Equation name is '_LC2_L21', type is buried 
_LC2_L21 = LCELL( _EQ082);
  _EQ082 = !mb3
         #  mb0 & !mb1
         # !mb1 & !mb2
         # !mb0 & !mb2;

-- Node name is ':1730' 
-- Equation name is '_LC8_L20', type is buried 
_LC8_L20 = LCELL( _EQ083);
  _EQ083 = !_LC4_L20 &  _LC5_L21
         #  _LC2_L21 & !_LC4_L20;

-- Node name is ':1737' 
-- Equation name is '_LC1_L20', type is buried 
_LC1_L20 = LCELL( _EQ084);
  _EQ084 =  _LC8_L20
         #  _LC7_L21
         #  _LC1_L21
         #  _LC4_L21;

-- Node name is '~1779~1' 
-- Equation name is '~1779~1', location is LC5_L21, type is buried.
-- synthesized logic cell 
_LC5_L21 = LCELL( _EQ085);
  _EQ085 =  mb0 &  mb1 &  mb2 & !mb3
         # !mb1 & !mb2 &  mb3
         # !mb0 & !mb2 &  mb3;

-- Node name is ':1785' 
-- Equation name is '_LC3_L21', type is buried 
_LC3_L21 = LCELL( _EQ086);
  _EQ086 =  mb0 & !mb1
         # !mb1 & !mb2
         #  mb0 & !mb2
         # !mb2 &  mb3
         # !mb1 & !mb3
         #  mb0 & !mb3
         #  mb2 & !mb3;

-- Node name is ':1812' 
-- Equation name is '_LC7_L20', type is buried 
_LC7_L20 = LCELL( _EQ087);
  _EQ087 = !mb1
         # !mb3
         # !mb0 &  mb2
         #  mb0 & !mb2;

-- Node name is ':1821' 
-- Equation name is '_LC2_L20', type is buried 
_LC2_L20 = LCELL( _EQ088);
  _EQ088 = !_LC6_L20 &  _LC7_L20
         #  _LC4_L20;

-- Node name is ':1835' 
-- Equation name is '_LC6_L21', type is buried 
_LC6_L21 = LCELL( _EQ089);
  _EQ089 =  _LC2_L20 & !_LC4_L21 & !_LC7_L21
         #  _LC1_L21 & !_LC7_L21;

-- Node name is ':1883' 
-- Equation name is '_LC8_L21', type is buried 
_LC8_L21 = LCELL( _EQ090);
  _EQ090 =  mb1 &  mb3
         #  mb2 &  mb3
         # !mb0 &  mb1
         # !mb0 & !mb2
         # !mb0 &  mb3;

-- Node name is ':1931' 
-- Equation name is '_LC1_L23', type is buried 
_LC1_L23 = LCELL( _EQ091);
  _EQ091 = !mb0 & !mb1
         #  mb1 &  mb3
         # !mb0 &  mb2
         # !mb0 &  mb3
         # !mb2 &  mb3
         # !mb1 &  mb2 & !mb3;

-- Node name is ':1956' 
-- Equation name is '_LC5_L20', type is buried 
_LC5_L20 = LCELL( _EQ092);
  _EQ092 = !mb2 &  mb3
         #  mb0 &  mb3
         #  mb1 &  mb3;

-- Node name is '~1974~1' 
-- Equation name is '~1974~1', location is LC1_L21, type is buried.
-- synthesized logic cell 
_LC1_L21 = LCELL( _EQ093);
  _EQ093 =  mb1 & !mb2 & !mb3;

-- Node name is '~1974~2' 
-- Equation name is '~1974~2', location is LC3_L20, type is buried.
-- synthesized logic cell 
_LC3_L20 = LCELL( _EQ094);
  _EQ094 =  _LC4_L20
         #  _LC4_L21
         #  _LC5_L20 & !_LC6_L20;

-- Node name is ':1979' 
-- Equation name is '_LC7_L24', type is buried 
_LC7_L24 = LCELL( _EQ095);
  _EQ095 =  _LC1_L21 & !_LC7_L21
         #  _LC3_L20 & !_LC7_L21;



Project Information                        g:\cpld_example\count60\count60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesi