📄 count60.rpt
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Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 1 8 0 0 0 0 8 0 0 1 0 8 8 3 8 8 1 8 8 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18/0
Total: 8 1 8 0 0 0 0 8 0 0 1 0 8 8 3 8 8 1 8 16 8 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 97/0
Device-Specific Information: g:\cpld_example\count60\count60.rpt
count60
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G ^ 0 0 0 0 inclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\cpld_example\count60\count60.rpt
count60
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
168 - - - 17 OUTPUT 0 1 0 0 outa0
167 - - - 16 OUTPUT 0 1 0 0 outa1
166 - - - 15 OUTPUT 0 1 0 0 outa2
164 - - - 14 OUTPUT 0 1 0 0 outa3
163 - - - 14 OUTPUT 0 1 0 0 outa4
162 - - - 13 OUTPUT 0 1 0 0 outa5
161 - - - 12 OUTPUT 0 1 0 0 outa6
177 - - - 24 OUTPUT 0 1 0 0 outb0
176 - - - 23 OUTPUT 0 1 0 0 outb1
175 - - - 22 OUTPUT 0 1 0 0 outb2
174 - - - 22 OUTPUT 0 1 0 0 outb3
173 - - - 21 OUTPUT 0 1 0 0 outb4
172 - - - 20 OUTPUT 0 1 0 0 outb5
170 - - - 19 OUTPUT 0 1 0 0 outb6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\cpld_example\count60\count60.rpt
count60
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 08 AND2 0 3 0 2 |LPM_ADD_SUB:314|addcore:adder|:143
- 3 - B 08 AND2 0 2 0 3 |LPM_ADD_SUB:314|addcore:adder|:147
- 1 - B 08 AND2 0 3 0 5 |LPM_ADD_SUB:314|addcore:adder|:155
- 8 - B 01 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:159
- 5 - B 01 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:167
- 7 - B 01 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:171
- 2 - B 01 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:179
- 6 - B 17 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:183
- 1 - B 17 AND2 0 4 0 2 |LPM_ADD_SUB:314|addcore:adder|:191
- 1 - B 20 AND2 0 2 0 3 |LPM_ADD_SUB:314|addcore:adder|:195
- 2 - B 20 AND2 0 3 0 3 |LPM_ADD_SUB:314|addcore:adder|:203
- 4 - B 20 AND2 0 3 0 3 |LPM_ADD_SUB:314|addcore:adder|:211
- 1 - B 03 AND2 0 3 0 3 |LPM_ADD_SUB:314|addcore:adder|:219
- 6 - B 03 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:223
- 7 - B 16 AND2 0 2 0 1 |LPM_ADD_SUB:838|addcore:adder|:55
- 5 - B 16 OR2 0 4 0 1 |LPM_ADD_SUB:838|addcore:adder|:69
- 7 - B 03 DFFE + 0 3 0 1 md24 (:16)
- 5 - B 03 DFFE + 0 3 0 2 md23 (:17)
- 4 - B 03 DFFE + 0 2 0 3 md22 (:18)
- 8 - B 03 DFFE + 0 3 0 2 md21 (:19)
- 2 - B 02 DFFE + 0 2 0 3 md20 (:20)
- 8 - B 20 DFFE + 0 3 0 2 md19 (:21)
- 7 - B 20 DFFE + 0 2 0 3 md18 (:22)
- 3 - B 20 DFFE + 0 3 0 2 md17 (:23)
- 6 - B 20 DFFE + 0 2 0 3 md16 (:24)
- 3 - B 17 DFFE + 0 2 0 2 md15 (:25)
- 7 - B 17 DFFE + 0 3 0 2 md14 (:26)
- 5 - B 17 DFFE + 0 3 0 3 md13 (:27)
- 8 - B 17 DFFE + 0 2 0 4 md12 (:28)
- 1 - B 01 DFFE + 0 3 0 2 md11 (:29)
- 6 - B 01 DFFE + 0 3 0 3 md10 (:30)
- 4 - B 01 DFFE + 0 2 0 4 md9 (:31)
- 3 - B 01 DFFE + 0 3 0 2 md8 (:32)
- 2 - B 19 DFFE + 0 3 0 3 md7 (:33)
- 1 - B 19 DFFE + 0 2 0 4 md6 (:34)
- 8 - B 08 DFFE + 0 3 0 1 md5 (:35)
- 7 - B 08 DFFE + 0 2 0 2 md4 (:36)
- 6 - B 08 DFFE + 0 2 0 1 md3 (:37)
- 5 - B 08 DFFE + 0 3 0 1 md2 (:38)
- 4 - B 08 DFFE + 0 2 0 2 md1 (:39)
- 2 - B 26 DFFE + 0 0 0 3 md0 (:40)
- 3 - B 19 DFFE + 0 1 0 8 f (:41)
- 2 - B 13 DFFE 0 4 0 14 ma3 (:42)
- 4 - B 16 DFFE 0 4 0 15 ma2 (:43)
- 3 - B 16 DFFE 0 3 0 16 ma1 (:44)
- 1 - B 13 DFFE 0 1 0 16 ma0 (:45)
- 6 - B 16 DFFE 0 4 0 15 mb3 (:46)
- 8 - B 16 DFFE 0 4 0 15 mb2 (:47)
- 6 - B 19 DFFE 0 4 0 16 mb1 (:48)
- 7 - B 19 DFFE 0 2 0 16 mb0 (:49)
- 4 - B 17 OR2 s 0 4 0 1 ~153~1
- 4 - B 19 OR2 s 0 3 0 1 ~153~2
- 3 - B 03 OR2 s 0 3 0 1 ~153~3
- 5 - B 20 OR2 s 0 4 0 1 ~153~4
- 2 - B 17 OR2 s 0 4 0 1 ~153~5
- 2 - B 03 OR2 s 0 4 0 1 ~153~6
- 8 - B 19 OR2 ! 0 4 0 25 :153
- 1 - B 16 AND2 0 4 0 6 :795
- 2 - B 16 OR2 ! 0 4 0 3 :813
- 6 - B 14 OR2 ! 0 4 0 1 :1095
- 4 - B 13 AND2 0 4 0 3 :1179
- 1 - B 14 OR2 ! 0 4 0 4 :1215
- 4 - B 11 OR2 0 4 1 0 :1220
- 8 - B 14 OR2 0 4 0 1 :1259
- 2 - B 14 OR2 0 4 1 0 :1266
- 5 - B 14 OR2 0 4 0 1 :1286
- 7 - B 14 OR2 s 0 2 0 2 ~1308~1
- 4 - B 14 OR2 s 0 4 0 1 ~1308~2
- 5 - B 13 OR2 0 4 1 0 :1314
- 8 - B 13 OR2 0 4 0 1 :1350
- 6 - B 13 OR2 0 4 1 0 :1364
- 1 - B 15 OR2 0 4 1 0 :1412
- 2 - B 15 OR2 0 4 0 1 :1445
- 3 - B 14 OR2 s 0 4 0 2 ~1449~1
- 5 - B 15 OR2 0 4 1 0 :1460
- 3 - B 13 OR2 0 4 0 1 :1493
- 7 - B 13 AND2 s 0 3 0 4 ~1503~1
- 7 - B 18 OR2 0 4 1 0 :1508
- 6 - L 20 OR2 ! 0 4 0 2 :1614
- 4 - L 20 OR2 s 0 4 0 3 ~1641~1
- 4 - L 21 AND2 0 4 0 3 :1650
- 7 - L 21 OR2 ! 0 4 0 3 :1686
- 5 - B 19 OR2 0 4 1 0 :1691
- 2 - L 21 OR2 0 4 0 1 :1712
- 8 - L 20 OR2 0 3 0 1 :1730
- 1 - L 20 OR2 0 4 1 0 :1737
- 5 - L 21 OR2 s 0 4 0 1 ~1779~1
- 3 - L 21 OR2 0 4 1 0 :1785
- 7 - L 20 OR2 0 4 0 1 :1812
- 2 - L 20 OR2 0 3 0 1 :1821
- 6 - L 21 OR2 0 4 1 0 :1835
- 8 - L 21 OR2 0 4 1 0 :1883
- 1 - L 23 OR2 0 4 1 0 :1931
- 5 - L 20 OR2 0 4 0 1 :1956
- 1 - L 21 AND2 s 0 3 0 3 ~1974~1
- 3 - L 20 OR2 s 0 4 0 1 ~1974~2
- 7 - L 24 OR2 0 3 1 0 :1979
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\cpld_example\count60\count60.rpt
count60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 26/208( 12%) 10/104( 9%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 11/104( 10%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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