twelveto1v.vhd

一个关于VHDL的cpld开发实验程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity twelveto1v is
port(finclk:in std_logic;
     outputa:out std_logic_vector(6 downto 0);
     outputb:out std_logic_vector(6 downto 0)
     );
end twelveto1v;
architecture arch_twelveto1 of twelveto1v is
     signal sa:std_logic_vector(3 downto 0);
     signal sb:std_logic_vector(3 downto 0);
     signal f:std_logic;
component fp
   port(inclk:in std_logic;
        outputf:out std_logic
        );
end component;
begin
u1:fp                                                                               
port map(inclk=>finclk,outputf=>f);
process(f)
begin
  if(rising_edge(f))then
    if(sa=2 and sb=1)then
      sa<="0001";
      sb<="0000";
    else
      if sa=9 then
        sa<="0000";
        sb<=sb+1;
      else
        sa<=sa+1;
      end if;
    end if;
  end if;
end process;
with sa select
outputa<="0110000"when"0001",  --1
         "1101101"when"0010",  --2
         "1111001"when"0011",  --3
         "0110011"when"0100",  --4
         "1011011"when"0101",  --5
         "1011111"when"0110",  --6
         "1110000"when"0111",  --7
         "1111111"when"1000",  --8
         "1111011"when"1001",  --9
         "1110111"when"1010",  --A
         "0011111"when"1011",  --B
         "1001110"when"1100",  --C
         "0111101"when"1101",  --D
         "1001111"when"1110",  --E
         "1000111"when"1111",  --F
         "1111110"when others; --0
with sb select
outputb<="0110000"when"0001",  --1
         "1101101"when"0010",  --2
         "1111001"when"0011",  --3
         "0110011"when"0100",  --4
         "1011011"when"0101",  --5
         "1011111"when"0110",  --6
         "1110000"when"0111",  --7
         "1111111"when"1000",  --8
         "1111011"when"1001",  --9
         "1110111"when"1010",  --A
         "0011111"when"1011",  --B
         "1001110"when"1100",  --C
         "0111101"when"1101",  --D
         "1001111"when"1110",  --E
         "1000111"when"1111",  --F
         "1111110"when others; --0
end arch_twelveto1;