twelveto1.rpt

一个关于VHDL的cpld开发实验程序

         #  va0 &  va1 & !va3
         #  va0 &  va2 & !va3
         #  va1 &  va2 & !va3
         # !va0 &  va3
         # !va0 & !va2
         #  va0 &  va1 &  va2;

-- Node name is ':345' from file "twelveto1.tdf" line 41, column 18
-- Equation name is '_LC1_K15', type is buried 
_LC1_K15 = LCELL( _EQ063);
  _EQ063 = !va0 &  va1 &  va2
         # !va0 &  va2 &  va3
         # !va0 & !va2 & !va3
         #  va0 &  va1 &  va3
         #  va1 & !va2 &  va3
         # !va1 &  va2 &  va3
         # !va0 & !va1 &  va3;

-- Node name is ':347' from file "twelveto1.tdf" line 41, column 20
-- Equation name is '_LC4_K15', type is buried 
_LC4_K15 = LCELL( _EQ064);
  _EQ064 = !va1 &  va2 & !va3
         # !va0 &  va2
         #  va1 &  va3
         # !va2 &  va3
         # !va0 &  va3
         # !va0 & !va1;

-- Node name is ':349' from file "twelveto1.tdf" line 41, column 22
-- Equation name is '_LC4_K18', type is buried 
_LC4_K18 = LCELL( _EQ065);
  _EQ065 = !va0 &  va1 &  va2
         # !va0 &  va1 & !va3
         #  va0 & !va1 &  va2
         #  va0 &  va1 & !va2
         #  va0 &  va3
         # !va2 &  va3
         # !va0 &  va2 & !va3;

-- Node name is ':352' from file "twelveto1.tdf" line 45, column 4
-- Equation name is '_LC3_K19', type is buried 
!_LC3_K19 = _LC3_K19~NOT;
_LC3_K19~NOT = LCELL( _EQ066);
  _EQ066 = !vb0 & !vb1 & !vb2 & !vb3;

-- Node name is ':362' from file "twelveto1.tdf" line 46, column 4
-- Equation name is '_LC8_K19', type is buried 
_LC8_K19 = LCELL( _EQ067);
  _EQ067 =  vb2
         #  vb3
         # !vb0
         #  vb1;

-- Node name is ':398' from file "twelveto1.tdf" line 49, column 4
-- Equation name is '_LC8_K24', type is buried 
!_LC8_K24 = _LC8_K24~NOT;
_LC8_K24~NOT = LCELL( _EQ068);
  _EQ068 = !vb0 & !vb1 &  vb2 & !vb3;

-- Node name is ':454' from file "twelveto1.tdf" line 53, column 4
-- Equation name is '_LC3_K24', type is buried 
!_LC3_K24 = _LC3_K24~NOT;
_LC3_K24~NOT = LCELL( _EQ069);
  _EQ069 = !vb0 & !vb1 & !vb2 &  vb3;

-- Node name is ':490' from file "twelveto1.tdf" line 55, column 4
-- Equation name is '_LC7_K24', type is buried 
!_LC7_K24 = _LC7_K24~NOT;
_LC7_K24~NOT = LCELL( _EQ070);
  _EQ070 = !vb0 &  vb1 & !vb2 &  vb3;

-- Node name is ':523' from file "twelveto1.tdf" line 57, column 4
-- Equation name is '_LC5_K19', type is buried 
!_LC5_K19 = _LC5_K19~NOT;
_LC5_K19~NOT = LCELL( _EQ071);
  _EQ071 = !vb0 & !vb1 &  vb2 &  vb3;

-- Node name is ':539' from file "twelveto1.tdf" line 58, column 12
-- Equation name is '_LC6_K19', type is buried 
_LC6_K19 = LCELL( _EQ072);
  _EQ072 = !vb0 & !vb1 & !vb3
         # !vb0 & !vb2
         #  vb0 &  vb1 & !vb3
         #  vb0 & !vb1 &  vb3
         # !vb2 & !vb3
         # !vb1 & !vb2;

-- Node name is ':541' from file "twelveto1.tdf" line 58, column 14
-- Equation name is '_LC1_K21', type is buried 
_LC1_K21 = LCELL( _EQ073);
  _EQ073 =  vb0 & !vb1
         #  vb2 & !vb3
         #  vb0 & !vb2
         # !vb2 &  vb3
         # !vb1 & !vb3
         #  vb0 & !vb3;

-- Node name is ':557' from file "twelveto1.tdf" line 59, column 16
-- Equation name is '_LC2_K22', type is buried 
_LC2_K22 = LCELL( _EQ074);
  _EQ074 = !_LC3_K24
         # !_LC3_K19
         #  _LC4_K19
         # !_LC5_K19;

-- Node name is ':572' from file "twelveto1.tdf" line 60, column 10
-- Equation name is '_LC7_K19', type is buried 
_LC7_K19 = LCELL( _EQ075);
  _EQ075 =  vb0 &  vb2 & !vb3
         # !vb1 & !vb2 &  vb3
         # !vb0 & !vb2
         #  vb0 &  vb1 &  vb2
         #  vb1 & !vb3
         # !vb0 &  vb3;

-- Node name is ':574' from file "twelveto1.tdf" line 60, column 18
-- Equation name is '_LC4_K21', type is buried 
_LC4_K21 = LCELL( _EQ076);
  _EQ076 = !vb0 & !vb2
         #  vb2 &  vb3
         # !vb0 &  vb1
         #  vb1 &  vb3;

-- Node name is ':576' from file "twelveto1.tdf" line 60, column 20
-- Equation name is '_LC2_K23', type is buried 
_LC2_K23 = LCELL( _EQ077);
  _EQ077 = !vb1 &  vb2 & !vb3
         # !vb2 &  vb3
         # !vb0 & !vb1 & !vb3
         # !vb0 & !vb1 &  vb2
         # !vb0 &  vb2 & !vb3
         #  vb1 &  vb3;

-- Node name is '~578~1' from file "twelveto1.tdf" line 60, column 22
-- Equation name is '~578~1', location is LC4_K19, type is buried.
-- synthesized logic cell 
_LC4_K19 = LCELL( _EQ078);
  _EQ078 =  vb0 & !vb1 &  vb3
         #  vb0 &  vb1 & !vb2
         #  vb0 & !vb2 &  vb3
         #  vb0 & !vb1 &  vb2
         # !vb0 &  vb1 &  vb2
         #  vb1 & !vb2 & !vb3;

-- Node name is '~578~2' from file "twelveto1.tdf" line 60, column 22
-- Equation name is '~578~2', location is LC6_K24, type is buried.
-- synthesized logic cell 
_LC6_K24 = LCELL( _EQ079);
  _EQ079 =  _LC5_K24 &  vb2 &  vb3
         #  _LC4_K19;

-- Node name is ':578' from file "twelveto1.tdf" line 60, column 22
-- Equation name is '_LC4_K24', type is buried 
_LC4_K24 = LCELL( _EQ080);
  _EQ080 =  _LC6_K24
         # !_LC7_K24
         # !_LC3_K24
         # !_LC8_K24;



Project Information                    g:\cpld_example\twelveto1\twelveto1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 58,161K