📄 twelveto1.rpt
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Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 9/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 1 0 7 8 0 8 0 0 0 0 0 0 0 8 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 1 8 2 2 0 0 1 8 0 2 1 1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 1 0 7 8 0 8 0 0 0 1 8 2 2 8 0 1 16 0 2 1 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82/0
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1.rpt
twelveto1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G ^ 0 0 0 0 inclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1.rpt
twelveto1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
161 - - - 12 OUTPUT 0 1 0 0 outa0
162 - - - 13 OUTPUT 0 1 0 0 outa1
163 - - - 14 OUTPUT 0 1 0 0 outa2
164 - - - 14 OUTPUT 0 1 0 0 outa3
166 - - - 15 OUTPUT 0 1 0 0 outa4
167 - - - 16 OUTPUT 0 1 0 0 outa5
168 - - - 17 OUTPUT 0 1 0 0 outa6
170 - - - 19 OUTPUT 0 1 0 0 outb0
172 - - - 20 OUTPUT 0 1 0 0 outb1
173 - - - 21 OUTPUT 0 1 0 0 outb2
174 - - - 22 OUTPUT 0 1 0 0 outb3
175 - - - 22 OUTPUT 0 1 0 0 outb4
176 - - - 23 OUTPUT 0 1 0 0 outb5
177 - - - 24 OUTPUT 0 1 0 0 outb6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1.rpt
twelveto1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - E 05 DFFE + 0 1 0 8 |fp:f1|f
- 2 - E 03 DFFE + 0 0 0 3 |fp:f1|fp0
- 4 - E 24 DFFE + 0 2 0 2 |fp:f1|fp1
- 5 - E 24 DFFE + 0 3 0 1 |fp:f1|fp2
- 6 - E 24 DFFE + 0 2 0 1 |fp:f1|fp3
- 7 - E 24 DFFE + 0 2 0 2 |fp:f1|fp4
- 8 - E 24 DFFE + 0 3 0 1 |fp:f1|fp5
- 7 - E 06 DFFE + 0 2 0 2 |fp:f1|fp6
- 5 - E 06 DFFE + 0 2 0 3 |fp:f1|fp7
- 4 - E 06 DFFE + 0 3 0 2 |fp:f1|fp8
- 2 - E 06 DFFE + 0 2 0 3 |fp:f1|fp9
- 3 - E 06 DFFE + 0 3 0 2 |fp:f1|fp10
- 2 - E 05 DFFE + 0 2 0 3 |fp:f1|fp11
- 6 - E 19 DFFE + 0 3 0 2 |fp:f1|fp12
- 8 - E 19 DFFE + 0 2 0 3 |fp:f1|fp13
- 7 - E 19 DFFE + 0 3 0 2 |fp:f1|fp14
- 5 - E 05 DFFE + 0 2 0 4 |fp:f1|fp15
- 7 - E 05 DFFE + 0 3 0 3 |fp:f1|fp16
- 8 - E 16 DFFE + 0 2 0 2 |fp:f1|fp17
- 7 - E 16 DFFE + 0 2 0 4 |fp:f1|fp18
- 6 - E 16 DFFE + 0 3 0 3 |fp:f1|fp19
- 5 - E 16 DFFE + 0 2 0 2 |fp:f1|fp20
- 8 - E 08 DFFE + 0 2 0 3 |fp:f1|fp21
- 7 - E 08 DFFE + 0 3 0 2 |fp:f1|fp22
- 6 - E 08 DFFE + 0 2 0 2 |fp:f1|fp23
- 5 - E 08 DFFE + 0 3 0 1 |fp:f1|fp24
- 1 - E 16 OR2 s 0 4 0 1 |fp:f1|~95~1
- 3 - E 08 OR2 s 0 3 0 1 |fp:f1|~95~2
- 2 - E 08 OR2 s 0 3 0 1 |fp:f1|~95~3
- 2 - E 19 OR2 s 0 4 0 1 |fp:f1|~95~4
- 4 - E 19 OR2 s 0 4 0 1 |fp:f1|~95~5
- 1 - E 19 OR2 s 0 4 0 1 |fp:f1|~95~6
- 1 - E 08 OR2 0 4 0 25 |fp:f1|:95
- 1 - E 24 AND2 0 3 0 2 |fp:f1|:109
- 3 - E 24 AND2 0 2 0 3 |fp:f1|:113
- 2 - E 24 AND2 0 3 0 3 |fp:f1|:121
- 6 - E 06 AND2 0 2 0 3 |fp:f1|:125
- 8 - E 06 AND2 0 3 0 3 |fp:f1|:133
- 1 - E 06 AND2 0 3 0 3 |fp:f1|:141
- 5 - E 19 AND2 0 3 0 3 |fp:f1|:149
- 3 - E 19 AND2 0 3 0 4 |fp:f1|:157
- 4 - E 05 AND2 0 3 0 1 |fp:f1|:165
- 3 - E 16 AND2 0 4 0 4 |fp:f1|:169
- 4 - E 16 AND2 0 3 0 1 |fp:f1|:177
- 2 - E 16 AND2 0 4 0 3 |fp:f1|:181
- 4 - E 08 AND2 0 3 0 2 |fp:f1|:189
- 1 - E 05 DFFE 0 1 0 12 va0
- 7 - K 13 DFFE 0 3 0 11 va1
- 5 - K 13 DFFE 0 4 0 10 va2
- 4 - K 13 DFFE 0 4 0 9 va3
- 3 - E 05 DFFE 0 3 0 14 vb0
- 2 - K 19 DFFE 0 3 0 13 vb1
- 1 - K 24 DFFE 0 3 0 14 vb2
- 2 - K 24 DFFE 0 4 0 13 vb3
- 1 - K 13 AND2 ! 0 4 0 5 :68
- 5 - K 24 AND2 0 2 0 3 :78
- 1 - K 19 OR2 0 3 0 4 :92
- 8 - K 13 AND2 0 2 0 1 :99
- 2 - K 13 OR2 0 4 0 2 :141
- 1 - K 14 OR2 s 0 4 0 1 ~310~1
- 2 - K 14 OR2 0 2 1 0 :310
- 6 - K 13 OR2 0 4 1 0 :312
- 3 - K 13 OR2 0 4 1 0 :328
- 1 - K 12 OR2 0 4 1 0 :343
- 1 - K 15 OR2 0 4 1 0 :345
- 4 - K 15 OR2 0 4 1 0 :347
- 4 - K 18 OR2 0 4 1 0 :349
- 3 - K 19 AND2 ! 0 4 0 1 :352
- 8 - K 19 OR2 0 4 0 1 :362
- 8 - K 24 AND2 ! 0 4 0 1 :398
- 3 - K 24 AND2 ! 0 4 0 2 :454
- 7 - K 24 AND2 ! 0 4 0 1 :490
- 5 - K 19 AND2 ! 0 4 0 1 :523
- 6 - K 19 OR2 0 4 1 0 :539
- 1 - K 21 OR2 0 4 1 0 :541
- 2 - K 22 OR2 0 4 1 0 :557
- 7 - K 19 OR2 0 4 1 0 :572
- 4 - K 21 OR2 0 4 1 0 :574
- 2 - K 23 OR2 0 4 1 0 :576
- 4 - K 19 OR2 s 0 4 0 2 ~578~1
- 6 - K 24 OR2 s 0 4 0 1 ~578~2
- 4 - K 24 OR2 0 4 1 0 :578
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\cpld_example\twelveto1\twelveto1.rpt
twelveto1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 21/208( 10%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 7/208( 3%) 9/104( 8%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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